... | @@ -21,7 +21,7 @@ other IP cores through a simple VHDL interface. |
... | @@ -21,7 +21,7 @@ other IP cores through a simple VHDL interface. |
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The drawing below depicts the internal modules of WRPC:
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The drawing below depicts the internal modules of WRPC:
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Detailed description see:
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Detailed description see:
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[G. Daniluk, T. Włostowski, White Rabbit: sub-nanoseconds
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[G. Daniluk, T. Włostowski, White Rabbit: sub-nanoseconds
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... | @@ -42,7 +42,7 @@ Altera GX PHYs is currently being implemented. |
... | @@ -42,7 +42,7 @@ Altera GX PHYs is currently being implemented. |
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The drawing below depicts the necessary external components to upgrade
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The drawing below depicts the necessary external components to upgrade
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an existing system:
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an existing system:
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The necessary external components are the fiber optic transceiver (SFP
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The necessary external components are the fiber optic transceiver (SFP
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module) and two digitally tunable clock generators (one for the main
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module) and two digitally tunable clock generators (one for the main
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... | @@ -55,7 +55,7 @@ address and calibration parameters). |
... | @@ -55,7 +55,7 @@ address and calibration parameters). |
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The table below shows the FPGA utilization summary (PRELIMINARY) of the
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The table below shows the FPGA utilization summary (PRELIMINARY) of the
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WRPC relevant resources only (Spartan-6, XC6SLX45T-3FGG484, ISE 13.4):
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WRPC relevant resources only (Spartan-6, XC6SLX45T-3FGG484, ISE 13.4):
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### More information:
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### More information:
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... | @@ -113,7 +113,7 @@ Scheduled features may include: |
... | @@ -113,7 +113,7 @@ Scheduled features may include: |
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-----
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-----
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Daniel Florin - 08 May 2012
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Daniel Florin - 09 May 2012
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