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# WRReferenceDesign
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# White Rabbit Node Reference Design
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The implementation of the WR-PTP protocol and appropriate network
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hardware is not a trivial task. The White Rabbit PTP Core (WRPC) was
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created to simplify the integration of the WR into both existing and
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embedded devices and systems. It is an HDL module that could be easily
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synthesized and used as a standalone WR interface inside a single FPGA
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chip or as an IP core in a larger design.
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WRPC implements an IEEE1588 ordinary clock capable of reaching
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sub-nanosecond accuracies and working both in Master and Slave modes. In
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master mode the WRPC uses externally-provided reference time and
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frequency to synchronize other WR compliant devices. When running in the
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slave mode, WRPC receives the timing information from a PTP master,
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synchronizes its internal clock and provides the timing information for
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other IP cores through a simple VHDL interface.
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Detailed description see [G. Daniluk, T. Włostowski, White Rabbit:
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sub-nanoseconds synchronization for embedded systems ,
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PTTI 2011](http://www.timeservers.eu/file_upl/PDF/Seminaria/Elproma%20CERN%20\(White_Rabbit\).pdf).
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This page briefly describes the hardware requirements to integrate the
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WRPC into two projects: Upgrading an existing system with WRPC and
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building a compact embedded solution.
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## Upgrading an existing system
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Only a few additional hardware components are required to upgrade an
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existing system with the WRPC, presuming the existing project already
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includes an appropriate FPGA and the required environment (power supply,
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configuration etc.). WRPC has been successfully tested with GTP and GTX
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transceivers of Xilinx's FPGAs (e.g. Spartan-6 LXT family). Support for
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Altera GX PHYs is currently being implemented.
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## Building a compact embedded solution
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This section describes the hardware of a standalone module which is a
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compact drop-in solution to achieve high-accuracy timing distribution
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with sub-ns synchronization based on WR.
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