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# SwitchMCH
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# An informal description of the MCH board
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For the foregoing discussion, please refer to the attached pdf (very
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informal and sketchy). The MCH is in fact made of a sandwich of 4
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PCBs:
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- The uplink board (aka the timing board) contains the uplink PHYs,
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the timing FPGA and its associated gear (DMTD, PLLs, clock
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fanouts...). The data links from the PHYs go directly to the main
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board through the sandwich connector, as do the RS232 debugging
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signals. The function of the timing FPGA is to take the rx\_clk,
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massage it and generate the compensated clock. Currently we're doing
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the phase shifting in WR slaves (i.e. in the uplink ports of
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switches). In the future, we intend to do the shifting in the
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masters, so as to reduce the complexity of slaves. Another important
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function of the timing board is to generate the DMTD clock, a clock
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offset in frequency by a tiny bit wrt the 125 MHz frame clock, and
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which is a key ingredient of DMTD-based phase detection and
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shifting. This clock is also distributed everywhere, including other
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AMC cards in the uTCA crate.
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- The main board. Packets hit the main FPGA from either uplink ports
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in the timing board or downlink ports in other AMCs. For reasons of
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clearness and laziness the connections to the backplane are not
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shown. In the main board there are eight PHYs sitting between the
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main FPGA and the \!GbE star in the backplane. All the routing logic
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is in the main FPGA. For storing routing tables, a ZBT RAM is used.
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The ARM9 embedded Linux CPU performs several tasks:
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- General service of the switch through its Fast Ethernet (100
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mb/s) RJ45 connection. So you can ping, ssh, etc.
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- Stuff too complicated for the main FPGA to handle (RSTP, PTP,
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etc.)
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- Configuration of FPGAs.
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- Other misc functions.
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- Two other boards to distribute signals to the backplane. The reason
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for this is that there are not enough contacts in a uTCA backplane
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connector to send all we want. The limitation is most severe in the
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MCH slot, where all stars converge. So uTCA deals with this problem
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by having 4 backplane connectors in the MCH slot, separated by a
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certain distance. By sandwiching PCBs and user appropriate spacers,
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we can send more signals to the backplane. So these extra two boards
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take signals from the other two boards through the sandwich
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connectors and put them on the backplane. These are mainly SMI (to
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be described later) and REF/DMTD clocks.
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In addition to the routing logic, the main FPGA also has the so-called
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SMI (Switch management Interface) links in LVDS to each slot in the
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backplane. This is used for things such as clock distribution, UTC,
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keeping routing tables up to date in all cards, etc. SMI operates
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synchronously to 125 MHz backplane reference clock and can be used to
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distribute event information such as PPS signal.
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The Watchdog CPU is another 32-bit microcontroller (ARM7 from Atmel)
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with two main tasks: uTCA crate management (acting as an \!I2C hub for
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controlling all slots using IPMI) and making sure we can't loose contact
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with the ARM9 or the Cyclone 3 after configuring with a broken binary.
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This is done with a watchdog mechanism, hence the name of this CPU.
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\-- Main.JavierSerrano - 19 Nov 2009
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\-- Main.TomaszWlostowski - 22 Nov 2009
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