... | ... | @@ -184,12 +184,12 @@ period 5 Oct (9am) to 8 Oct (6pm). |
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</tr>
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<tr class="even">
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<td>16:30 - 16:45</td>
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<td>DMTD clock generation using FPGA internal PLLs</td>
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<td>[DMTD clock generation using FPGA internal PLLs](https://www.ohwr.org/5898)</td>
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<td>Hongming Li</td>
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</tr>
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<tr class="odd">
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<td>16:45 - 17:00</td>
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<td>WR development and deployment for the LHAASO project</td>
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<td>[WR development and deployment for the LHAASO project](https://www.ohwr.org/5897)</td>
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<td>Hongming Li</td>
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</tr>
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<tr class="even">
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