... | @@ -5,13 +5,17 @@ crate when only the switch functionality of the MCH is required. |
... | @@ -5,13 +5,17 @@ crate when only the switch functionality of the MCH is required. |
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Features:
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Features:
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\- replaces the microTCA crate for switch-only applications. MCH +
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\- replaces the microTCA crate for switch-only applications.
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backplane = complete 10-port WR switch.
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\- provides 8 downlink ports with SFP sockets
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\- provides 8 downlink ports with SFP sockets
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\- provides PHY autocalibration (not supported by the MCH) on downlink
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\- provides PHY autocalibration (not supported by the MCH) on downlink
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ports
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ports
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Mini-backplane + MCH together = standalone 10-port switch, as shown
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below:
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![](/uploads/19d47978b9191250148532cc873fee9d/mini_backplane_panel.jpg)
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The drawing below shows the block diagram of the mini
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The drawing below shows the block diagram of the mini
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backplane:
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backplane:
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... | @@ -47,7 +51,7 @@ provides: |
... | @@ -47,7 +51,7 @@ provides: |
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### SFP assemblies
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### SFP assemblies
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There are 8 SFP assemblies, each of them including:
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There are 8 SFP assemblies, each of them having:
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- an SFP socket
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- an SFP socket
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- 2 status LEDs
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- 2 status LEDs
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... | @@ -55,7 +59,56 @@ There are 8 SFP assemblies, each of them including: |
... | @@ -55,7 +59,56 @@ There are 8 SFP assemblies, each of them including: |
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- I2C I/O expander for controlling the LEDs, cal. buffers and SFP
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- I2C I/O expander for controlling the LEDs, cal. buffers and SFP
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lines
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lines
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Below there is a block diagram of a single SFP assemly:
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Below there is a block diagram of a single SFP
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assemly:
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![](/uploads/cc5629df917a89d78e3e399484d8b05c/mini_backplane_sfp_assembly.jpg)
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The calibration buffers are placed very close to the SFP connector pins
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to avoid making stubs. The outputs of the buffers are connected together
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between two adjacent SFPs (e.g. SFP0 + SFP1, SFP2 + SFP3, ...) to avoid
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excessively long stubs on the feedback trace. Since the buffer outputs
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are tri-stated, it makes a nice and cheap multiplexer suitable for the
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calibration of the PHY asymmetry.
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All the digital lines (except for the SFP builtin I2C memory) are
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controlled by an 8-bit I2C GPIO expander (PCA9534):
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- P0: Link LED
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- P1: Status LED
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- P2: SFP Tx disable
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- P3: SFP Tx fault
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- P4: Calibration feedback enable for TX path
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- P5: Calibration feedback enable for RX path
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- P6: SFP loss-of-signal
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- P7: SFP detect
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Calibration feedback lines from SFP0+1, SFP2+3, SFP4+5, SFP6+7 are again
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multiplexed by another set of LVDS buffers, controlled by a separate I2C
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expander (PCA9534A).
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h4: I2C Logic
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Apart from the SFP assembly I/O expanders, there are 2 additional I2C
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chips:
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- 8-port I2C hub - PCA9548A (for multiplexing access to the SFP
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identification memories which have identical addresses)
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- 8-port I2C GPIO - PCA9535A for controlling layer2 calibration
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feedback muxes
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I2C peripheral address map:
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- port 0 GPIO: 0x40 (with IRQ line)
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- port 1 GPIO: 0x42 (with IRQ line)
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- port 2 GPIO: 0x44 (with IRQ line)
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- port 3 GPIO: 0x46 (with IRQ line)
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- port 4 GPIO: 0x48 (with IRQ line)
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- port 5 GPIO: 0x4a (with IRQ line)
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- port 6 GPIO: 0x4c (with IRQ line)
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- port 7 GPIO: 0x4e (with IRQ line)
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- calibration mux GPIO: 0x70
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- I2C HUB: 0xe0
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... | | ... | |