Description
The Wishbone serializer core helps to solve the problem of accessing a Wishbone slave in one Xilinx Spartan 6 FPGA from a Wishbone master in another Spartan 6 in a transparent way. Both FPGAs are connected by two Xilinx Gb serial links, one in each direction. In order to cope with the high latency and still maintain a good throughput, Wishbone pipelined access mode is used.
Documentation
Status
Date | Event |
01-10-2010 | Project start. |
12-11-2010 | document#36 published |
15-12-2010 | Order for development placed. |
Javier Serrano, Erik van der Bij - 13-Jan-2011