... | ... | @@ -16,7 +16,7 @@ Wishbone communication between two FPGA's. |
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The Wishbone Serializer core is in a working state, but still has a bug
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that seems to appear only when the clocks on both sides differ largely
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in frequency. This is documented in
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[Issue 623](https://www.ohwr.org/project/wb-serializer-core/issues/2).
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[Issue 623](https://www.ohwr.org/work_packages/623).
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### Q: Are the reset signals asserted low or high?
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