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# Frequently Asked Questions Wishbone Serializer Core
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## Synthesis
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### Q: Inside the WB serializer core, the "after" construct is widely used. Is it synthesizable?
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A: No, the "after" construct is ignored by the synthesizer. The VHDL
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simulators like ModelSim recognize it.
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It can be used to add a delay to a signal and make it change after the
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clock's rising edge. The waveform will be clearer
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but it is better not mixing constructs for simulation and constructs for
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synthesis.
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h2 Design
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### Q: Are the reset signals asserted low or high?
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A: The rst\_i is asserted low. The gt\_reset\_in\_i is asserted high.
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-----
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1 November 2012
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