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The Wishbone serializer core helps to solve the problem of accessing a
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The Wishbone serializer core helps to solve the problem of accessing a
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Wishbone slave in one Xilinx Spartan 6 FPGA from a Wishbone master in
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Wishbone slave in one Xilinx Spartan 6 FPGA from a Wishbone master in
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another Spartan 6 in a transparent way. Both FPGAs are connected by
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another Spartan 6 in a transparent way. Both FPGAs are connected by two
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Xilinx Gb serial links. In order to cope with the high latency and still
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Xilinx Gb serial links, one in each direction. In order to cope with the
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maintain a good throughput, Wishbone pipelined access mode is
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high latency and still maintain a good throughput, Wishbone pipelined
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access mode is
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used.
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used.
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![](/uploads/b801b7d5e9cea5577dd7265d8d884a3f/block-RXTX_small.png)
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![](/uploads/b801b7d5e9cea5577dd7265d8d884a3f/block-RXTX_small.png)
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# Work so far
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-----
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# Documentation
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- [Document](/project/wb-serializer-core/wikis/Documents/Technical-Specification)
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-----
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# Status
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<table>
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<table>
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<tbody>
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<tbody>
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... | @@ -25,9 +34,17 @@ used. |
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<td>12-11-2010</td>
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<td>12-11-2010</td>
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<td>document#36 published</td>
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<td>document#36 published</td>
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</tr>
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</tr>
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<tr class="even">
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<td>15-12-2010</td>
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<td><a href="https://edh.cern.ch/Document/SupplyChain/DAI/4532896">Order</a> for development placed.</td>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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-----
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Javier Serrano, Erik van der Bij - 13-Jan-2011
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### Files
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### Files
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... | | ... | |