... | @@ -4,9 +4,10 @@ The Wishbone serializer core helps to solve the problem of accessing a |
... | @@ -4,9 +4,10 @@ The Wishbone serializer core helps to solve the problem of accessing a |
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Wishbone slave in one Xilinx Spartan 6 FPGA from a Wishbone master in
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Wishbone slave in one Xilinx Spartan 6 FPGA from a Wishbone master in
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another Spartan 6 in a transparent way. Both FPGAs are connected by
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another Spartan 6 in a transparent way. Both FPGAs are connected by
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Xilinx Gb serial links. In order to cope with the high latency and still
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Xilinx Gb serial links. In order to cope with the high latency and still
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maintain a good throughput, Wishbone pipelined access mode is used.
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maintain a good throughput, Wishbone pipelined access mode is
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used.
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block-RXTX.png
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![](/uploads/b801b7d5e9cea5577dd7265d8d884a3f/block-RXTX_small.png)
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# Work so far
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# Work so far
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