... | ... | @@ -6,6 +6,8 @@ another Spartan 6 in a transparent way. Both FPGAs are connected by |
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Xilinx Gb serial links. In order to cope with the high latency and still
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maintain a good throughput, Wishbone pipelined access mode is used.
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block-RXTX.png
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# Work so far
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<table>
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