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# Description
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The Wishbone serializer core helps to solve the problem of accessing a
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Wishbone slave in one Xilinx Spartan 6 FPGA from a Wishbone master in
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another Spartan 6 in a transparent way. Both FPGAs are connected by
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Xilinx Gb serial links. In order to cope with the high latency and still
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maintain a good throughput, Wishbone pipelined access mode is used.
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# Work so far
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>01-10-2010</td>
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<td>Project start.</td>
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</tr>
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<tr class="odd">
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<td>12-11-2010</td>
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<td>document#36 published</td>
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</tr>
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</tbody>
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</table>
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### Files
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* [block-RXTX_small.png](/uploads/b801b7d5e9cea5577dd7265d8d884a3f/block-RXTX_small.png)
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* [Test_vme64x_WBserializer.png](/uploads/4bc76a264d01eebce3aa67acb6754ca3/Test_vme64x_WBserializer.png)
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* [ChipScope_wbserializer_bug.jpg](/uploads/dee81dabd49c380edb6a78e111235cbd/ChipScope_wbserializer_bug.jpg) |
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