... | ... | @@ -5,8 +5,11 @@ Wishbone slave in one Xilinx Spartan 6 FPGA from a Wishbone master in |
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another Spartan 6 in a transparent way. Both FPGAs are connected by two
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Xilinx Gb serial links, one in each direction. In order to cope with the
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high latency and still maintain a good throughput, Wishbone pipelined
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access mode is
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used.
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access mode is used. The main usage would be for use on the [VFC VME FMC
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carrier board](https://www.ohwr.org/project/fmc-vme-carrier/wiki).
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*This project is on
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hold.**
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![](/uploads/b801b7d5e9cea5577dd7265d8d884a3f/block-RXTX_small.png)
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... | ... | @@ -65,12 +68,16 @@ used. |
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<td>01-11-2012</td>
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<td>Additional tests at CERN show that no flow control is implemented, loosing data in certain circumstances.</td>
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</tr>
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<tr class="odd">
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<td>04-12-2012</td>
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<td><em>Project on hold.</em> Not needed for SVEC carrier and users of VFC have other solutions.</td>
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</tr>
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</tbody>
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</table>
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-----
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Javier Serrano, Erik van der Bij - 1 November 2012
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Javier Serrano, Erik van der Bij - 4 December 2012
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... | ... | |