... | @@ -55,6 +55,10 @@ Tag) |
... | @@ -55,6 +55,10 @@ Tag) |
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- [Block
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- [Block
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diagrams](https://www.ohwr.org/project/vxs-dsp-fmc-carrier/wikis/documents)
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diagrams](https://www.ohwr.org/project/vxs-dsp-fmc-carrier/wikis/documents)
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- The design may use different [HDL Core
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lib](https://www.ohwr.org/project/hdl-core-lib/) designs such as the
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[VME64x](https://www.ohwr.org/project/vme64x-core) and [Wishbone
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serialiser](https://www.ohwr.org/project/wb-serializer-core) cores.
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-----
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-----
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... | @@ -74,12 +78,20 @@ Tag) |
... | @@ -74,12 +78,20 @@ Tag) |
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<td>13-09-2010</td>
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<td>13-09-2010</td>
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<td>Start of design. Design will partially be based on the [VME FMC carrier](https://www.ohwr.org/project/fmc-vme-carrier).</td>
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<td>Start of design. Design will partially be based on the [VME FMC carrier](https://www.ohwr.org/project/fmc-vme-carrier).</td>
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</tr>
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</tr>
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<tr class="even">
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<td>06-12-2010</td>
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<td>Start of schematics design.</td>
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</tr>
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<tr class="odd">
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<td>13-01-2011</td>
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<td>PCB layout start should start by the end of February 2011.</td>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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-----
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-----
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John Molendijk, Erik van der Bij - 13 September 2010
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John Molendijk, Erik van der Bij - 13 Jan 2011
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