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# PCI-Express to VME bridge
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# PCI-Express to VME bridge
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This wiki page describes the PCI-Express to VME bridge HDL module. It was originally implemented by [MEN Mikro Elektronik
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This wiki page describes the PCI-Express to VME bridge HDL module. It was originally implemented by [MEN Mikro Elektronik GmbH](https://www.men.de/) on the [A25 SBC](https://www.duagon.com/products/details/a25/) and later open-sourced in the context of the CERN's VME Single Board Computers supply contract.
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GmbH](https://www.men.de/) on the [A25 SBC](https://www.duagon.com/products/details/a25/) and later open-sourced in the context of the CERN's VME Single Board Computers supply contract.
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The PCIe-to-VME bridge translates the read and write operations in the
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The PCIe-to-VME bridge translates the read and write operations in the
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PCIe address space to read and write transactions on the VME bus. It
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PCIe address space to read and write transactions on the VME bus. It
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acts as a PCIe Endpoint on one side and VME bus Master on the other. The
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acts as a **PCIe Endpoint** on one side and **VME bus Master** on the other. The
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bridge can generate VME single cycles and block transfers. The following
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bridge can generate VME single cycles and block transfers. The following
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access types are currently supported:
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access types are currently supported:
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... | @@ -26,6 +25,8 @@ write the CR/CSR configuration space of VME slaves installed in the same |
... | @@ -26,6 +25,8 @@ write the CR/CSR configuration space of VME slaves installed in the same |
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crate. However, none of the fast transfer modes (2eVME, 2eSST) is
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crate. However, none of the fast transfer modes (2eVME, 2eSST) is
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currently implemented.
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currently implemented.
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If you're looking for a VME-bus Slave, see the project [VME64x to Wishbone Core](https://ohwr.org/project/vme64x-core/wikis).
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## Supported FPGA platforms
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## Supported FPGA platforms
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|**Manufacturer**|**Family**|**Hardware board**|**Synthesized FPGA bitstream**|
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|**Manufacturer**|**Family**|**Hardware board**|**Synthesized FPGA bitstream**|
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... | @@ -129,7 +130,13 @@ SRAM modules. |
... | @@ -129,7 +130,13 @@ SRAM modules. |
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| 02-2018 | PCIe-VME64x bridge HDL and drivers are validated |
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| 02-2018 | PCIe-VME64x bridge HDL and drivers are validated |
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| 04-2018 | MEN A25 Single Board Computer board declared operational at CERN |
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| 04-2018 | MEN A25 Single Board Computer board declared operational at CERN |
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| 05-2018 | Version 3.15 of HDL released with improvements for BLT and MBLT performance |
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| 05-2018 | Version 3.15 of HDL released with improvements for BLT and MBLT performance |
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| 07-2022 | Plans to extend the core to support 2eSST cycles |
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---
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11 July 2022
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### Files
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### Files
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* [pcie-vme-hdl.png](/uploads/de3a50030fa9acb647827501af06eebb/pcie-vme-hdl.png)
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* [pcie-vme-hdl.png](/uploads/de3a50030fa9acb647827501af06eebb/pcie-vme-hdl.png)
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