... | ... | @@ -26,10 +26,26 @@ added in the VME64x extensions. It is able to use the geographical |
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addressing pins and generate a special type of A24 access to read and
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write the CR/CSR configuration space of VME slaves installed in the same
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crate. However, none of the fast transfer modes (2eVME, 2eSST) is
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currently
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implemented.
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currently implemented.
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### HDL architecture
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## Supported FPGA platforms
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Manufacturer </b></td>
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<td><b> Family </b></td>
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<td><b> Hardware board </b></td>
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</tr>
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<tr class="even">
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<td>Intel</td>
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<td>Cyclone IV</td>
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<td>MEN A25 VME Single Board Computer</td>
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</tr>
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</tbody>
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</table>
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# HDL architecture
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![](/uploads/de3a50030fa9acb647827501af06eebb/pcie-vme-hdl.png)
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... | ... | @@ -41,17 +57,17 @@ into several VHDL modules communicating together through the central |
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function and can either control other modules (is a Wishbone Master), be
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controlled (is a Wishbone Slave) or have both interfaces:
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- *PCIe2WB* - PCI Express x4 version 1.1 Endpoint with both WB Master
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and WB Slave interface
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- *VMEbus* - VME Master with both WB Master (for DMA transfers) and WB
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Slave (for single cycle accesses) interface
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- *Flash* - WB Slave module that interfaces the Flash chip outside the
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FPGA
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- *SRAM* - WB Slave module that interfaces the SRAM chip outside the
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FPGA
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- *Version ROM* - WB Slave module with FPGA memory blocks initialized
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at synthesis time with various information about the firmware (the
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so called chameleon table)
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- ***PCIe2WB*** - PCI Express x4 version 1.1 Endpoint with both WB
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Master and WB Slave interface
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- ***VMEbus*** - VME Master with both WB Master (for DMA transfers)
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and WB Slave (for single cycle accesses) interface
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- ***Flash*** - WB Slave module that interfaces the Flash chip outside
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the FPGA
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- ***SRAM*** - WB Slave module that interfaces the SRAM chip outside
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the FPGA
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- ***Version ROM*** - WB Slave module with FPGA memory blocks
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initialized at synthesis time with various information about the
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firmware (the so called chameleon table)
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The ***PCIe2WB*** module is in fact a wrapper for the Intel
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auto-generated IP core. This IP core customizes a PCI Express IP block
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... | ... | @@ -144,23 +160,6 @@ transferred word in the block, e.g. for transferring data words to SRAM. |
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The source and destination device can be any of of VME bus, PCIe2WB or
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SRAM modules.
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|
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### Supported FPGA platforms
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr class="odd">
|
|
|
<td><b> Manufacturer </b></td>
|
|
|
<td><b> Family </b></td>
|
|
|
<td><b> Hardware board </b></td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>Intel</td>
|
|
|
<td>Cyclone IV</td>
|
|
|
<td>MEN A25 VME Single Board Computer</td>
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|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
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# Documentation
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# Contacts
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... | ... | |