This project defines the coding style for VHDL files and provides a tool
to check the rules.
A text document contains a list of rules, like:
==== [PortsName] [M] Ports namePorts name must be in lower case (as ruled by Identifiers), but must also havea suffix:* '_i' for normal input.* '_o' for normal output.* '_b' for bidirectional port.The suffix must be the last one.Reason: Helps to specify the purpose of a port, makes the dataflow moreobvious.
A tool has been developed to automatically enforce the rules. For this
library ieee;use ieee.std_logic_1164.all;entity example is port (clk_i : in std_logic; incorrect : out std_logic);end example;
The tool will generate this message for the above rule:
./ex1.vhdl:6:9: [PortsName] out port 'incorrect' must end with '_o'