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TDC core
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7c5526f9
Commit
7c5526f9
authored
Aug 01, 2011
by
Sebastien Bourdeauducq
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Remove default generic values
parent
b079fdd3
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2 changed files
with
2 additions
and
2 deletions
+2
-2
tdc_delayline.vhd
core/tdc_delayline.vhd
+1
-1
tdc_lbc.vhd
core/tdc_lbc.vhd
+1
-1
No files found.
core/tdc_delayline.vhd
View file @
7c5526f9
...
...
@@ -25,7 +25,7 @@ use UNISIM.vcomponents.all;
entity
tdc_delayline
is
generic
(
g_WIDTH
:
positive
:
=
4
-- number of CARRY4 elements
g_WIDTH
:
positive
-- number of CARRY4 elements
);
port
(
clk_sample_i
:
in
std_logic
;
...
...
core/tdc_lbc.vhd
View file @
7c5526f9
...
...
@@ -24,7 +24,7 @@ entity tdc_lbc is
generic
(
-- Number of output bits.
-- The number of input bits is 2^g_N-1.
g_N
:
positive
:
=
4
g_N
:
positive
);
port
(
polarity_i
:
in
std_logic
;
...
...
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