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TDC core
Commit 6896864b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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working on the plan B, WIP

parent c9d9b7d6
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core/Manifest.py deleted 100644 → 0
View file @ c9d9b7d6
files = [
"tdc_controller.vhd", "tdc_freqc.vhd", "tdc_psync.vhd",
"tdc_channelbank.vhd", "tdc_delayline.vhd", "tdc_lbc.vhd", "tdc_ringosc.vhd",
"tdc_channel.vhd", "tdc_divider.vhd", "tdc_package.vhd", "tdc.vhd"
];
core/tdc_channel.vhd deleted 100644 → 0
View file @ c9d9b7d6
-------------------------------------------------------------------------------
-- TDC Core / CERN
-------------------------------------------------------------------------------
--
-- unit name: tdc_channel
--
-- author: Sebastien Bourdeauducq, sebastien@milkymist.org
--
-- description: Per-channel processing
--
-- references: http://www.ohwr.org/projects/tdc-core
--
-------------------------------------------------------------------------------
-- last changes:
-- 2011-11-07 SB Pre-inversion
-- 2011-10-25 SB Disable ring oscillator on reset
-- 2011-08-03 SB Created file
-------------------------------------------------------------------------------
-- Copyright (C) 2011 CERN
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, version 3 of the License.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- DESCRIPTION:
-- This contains the elements needed for each channel:
-- * Delay line
-- * Encoder
-- * LUT
-- * Deskew stage
-- * Online calibration ring oscillator
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tdc_package.all;
use work.genram_pkg.all;
entity tdc_channel is
generic(
-- Number of CARRY4 elements.
g_CARRY4_COUNT : positive;
-- Number of raw output bits.
g_RAW_COUNT : positive;
-- Number of fractional part bits.
g_FP_COUNT : positive;
-- Number of coarse counter bits.
g_COARSE_COUNT : positive;
-- Length of the ring oscillator.
g_RO_LENGTH : positive
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
-- Coarse counter and deskew inputs.
coarse_i : in std_logic_vector(g_COARSE_COUNT-1 downto 0);
deskew_i : in std_logic_vector((g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
-- Signal input.
signal_i : in std_logic;
calib_i : in std_logic;
calib_sel_i : in std_logic;
-- Detection outputs.
detect_o : out std_logic;
polarity_o : out std_logic;
raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
fp_o : out std_logic_vector((g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
-- LUT access.
lut_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
lut_we_i : in std_logic;
lut_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0);
lut_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0);
-- Calibration ring oscillator.
ro_en_i : in std_logic;
ro_clk_o : out std_logic
);
end entity;
architecture rtl of tdc_channel is
signal calib_sel_d : std_logic;
signal muxed_signal : std_logic;
signal inv_signal : std_logic;
signal taps : std_logic_vector(4*g_CARRY4_COUNT-1 downto 0);
signal ipolarity : std_logic;
signal polarity : std_logic;
signal polarity_d1 : std_logic;
signal polarity_d2 : std_logic;
signal detect_d1 : std_logic;
signal raw : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal raw_d1 : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal raw_d2 : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal lut : std_logic_vector(g_FP_COUNT-1 downto 0);
signal ro_en : std_logic;
begin
-- register calibration select signal to avoid glitches
process(clk_i)
begin
if rising_edge(clk_i) then
calib_sel_d <= calib_sel_i;
end if;
end process;
with calib_sel_d select
muxed_signal <= calib_i when '1', signal_i when others;
inv_signal <= muxed_signal xor not ipolarity;
cmp_delayline: tdc_delayline
generic map(
g_WIDTH => g_CARRY4_COUNT
)
port map(
clk_i => clk_i,
reset_i => reset_i,
signal_i => inv_signal,
taps_o => taps
);
cmp_lbc: tdc_lbc
generic map(
g_N => g_RAW_COUNT,
g_NIN => g_CARRY4_COUNT*4,
g_IGNORE => 2
)
port map(
clk_i => clk_i,
reset_i => reset_i,
d_i => taps,
ipolarity_o => ipolarity,
polarity_o => polarity,
count_o => raw
);
cmp_lut: generic_dpram
generic map(
g_data_width => g_FP_COUNT,
g_size => 2**g_RAW_COUNT,
g_with_byte_enable => false,
g_addr_conflict_resolution => "read_first",
g_init_file => "",
g_dual_clock => false
)
port map(
clka_i => clk_i,
clkb_i => '0',
wea_i => '0',
bwea_i => (others => '0'),
aa_i => raw,
da_i => (others => '0'),
qa_o => lut,
web_i => lut_we_i,
bweb_i => (others => '0'),
ab_i => lut_a_i,
db_i => lut_d_i,
qb_o => lut_d_o
);
cmp_ringosc: tdc_ringosc
generic map(
g_LENGTH => g_RO_LENGTH
)
port map(
en_i => ro_en,
clk_o => ro_clk_o
);
ro_en <= ro_en_i and not reset_i;
detect_d1 <= polarity_d1 xor polarity_d2;
process(clk_i)
begin
if rising_edge(clk_i) then
if reset_i = '1' then
detect_o <= '0';
polarity_d1 <= '1';
polarity_d2 <= '1';
raw_d1 <= (others => '0');
raw_d2 <= (others => '0');
else
detect_o <= detect_d1;
polarity_d1 <= polarity;
raw_d1 <= raw;
if detect_d1 = '1' then
polarity_d2 <= polarity_d1;
raw_d2 <= raw_d1;
end if;
end if;
end if;
end process;
polarity_o <= polarity_d2;
raw_o <= raw_d2;
-- Combine coarse counter value and deskew.
process(clk_i)
begin
if rising_edge(clk_i) then
if reset_i = '1' then
fp_o <= (others => '0');
else
if detect_d1 = '1' then
fp_o <= std_logic_vector(
unsigned(coarse_i & (lut'range => '0'))
- unsigned(lut)
+ unsigned(deskew_i));
end if;
end if;
end if;
end process;
end architecture;
core/tdc_ordertaps.vhd deleted 100644 → 0
View file @ c9d9b7d6
-- This file was autogenerated by ordertaps.py
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tdc_package.all;
entity tdc_ordertaps is
generic(
g_WIDTH: positive
);
port(
unsorted_i : in std_logic_vector(4*g_WIDTH-1 downto 0);
sorted_o : out std_logic_vector(4*g_WIDTH-1 downto 0)
);
end entity;
architecture rtl of tdc_ordertaps is
begin
sorted_o(0) <= unsorted_i(0); -- 0.843 ns
sorted_o(1) <= unsorted_i(1); -- 0.893 ns
sorted_o(2) <= unsorted_i(2); -- 0.894 ns
sorted_o(3) <= unsorted_i(3); -- 0.943 ns
sorted_o(4) <= unsorted_i(4); -- 0.965 ns
sorted_o(5) <= unsorted_i(5); -- 1.021 ns
sorted_o(6) <= unsorted_i(7); -- 1.023 ns
sorted_o(7) <= unsorted_i(6); -- 1.037 ns
sorted_o(8) <= unsorted_i(8); -- 1.046 ns
sorted_o(9) <= unsorted_i(9); -- 1.102 ns
sorted_o(10) <= unsorted_i(11); -- 1.104 ns
sorted_o(11) <= unsorted_i(10); -- 1.118 ns
sorted_o(12) <= unsorted_i(12); -- 1.128 ns
sorted_o(13) <= unsorted_i(13); -- 1.184 ns
sorted_o(14) <= unsorted_i(15); -- 1.186 ns
sorted_o(15) <= unsorted_i(14); -- 1.200 ns
sorted_o(16) <= unsorted_i(16); -- 1.209 ns
sorted_o(17) <= unsorted_i(17); -- 1.265 ns
sorted_o(18) <= unsorted_i(19); -- 1.267 ns
sorted_o(19) <= unsorted_i(18); -- 1.281 ns
sorted_o(20) <= unsorted_i(20); -- 1.290 ns
sorted_o(21) <= unsorted_i(21); -- 1.346 ns
sorted_o(22) <= unsorted_i(23); -- 1.348 ns
sorted_o(23) <= unsorted_i(22); -- 1.362 ns
sorted_o(24) <= unsorted_i(24); -- 1.448 ns
sorted_o(25) <= unsorted_i(25); -- 1.504 ns
sorted_o(26) <= unsorted_i(27); -- 1.506 ns
sorted_o(27) <= unsorted_i(26); -- 1.520 ns
sorted_o(28) <= unsorted_i(28); -- 1.525 ns
sorted_o(29) <= unsorted_i(29); -- 1.581 ns
sorted_o(30) <= unsorted_i(31); -- 1.583 ns
sorted_o(31) <= unsorted_i(30); -- 1.597 ns
sorted_o(32) <= unsorted_i(32); -- 1.602 ns
sorted_o(33) <= unsorted_i(33); -- 1.658 ns
sorted_o(34) <= unsorted_i(35); -- 1.660 ns
sorted_o(35) <= unsorted_i(34); -- 1.674 ns
sorted_o(36) <= unsorted_i(36); -- 1.678 ns
sorted_o(37) <= unsorted_i(37); -- 1.734 ns
sorted_o(38) <= unsorted_i(39); -- 1.736 ns
sorted_o(39) <= unsorted_i(38); -- 1.750 ns
sorted_o(40) <= unsorted_i(40); -- 1.755 ns
sorted_o(41) <= unsorted_i(41); -- 1.811 ns
sorted_o(42) <= unsorted_i(43); -- 1.813 ns
sorted_o(43) <= unsorted_i(42); -- 1.827 ns
sorted_o(44) <= unsorted_i(44); -- 1.832 ns
sorted_o(45) <= unsorted_i(45); -- 1.888 ns
sorted_o(46) <= unsorted_i(47); -- 1.890 ns
sorted_o(47) <= unsorted_i(46); -- 1.904 ns
sorted_o(48) <= unsorted_i(48); -- 1.910 ns
sorted_o(49) <= unsorted_i(49); -- 1.966 ns
sorted_o(50) <= unsorted_i(51); -- 1.968 ns
sorted_o(51) <= unsorted_i(50); -- 1.982 ns
sorted_o(52) <= unsorted_i(52); -- 1.988 ns
sorted_o(53) <= unsorted_i(53); -- 2.044 ns
sorted_o(54) <= unsorted_i(55); -- 2.046 ns
sorted_o(55) <= unsorted_i(54); -- 2.060 ns
sorted_o(56) <= unsorted_i(56); -- 2.095 ns
sorted_o(57) <= unsorted_i(57); -- 2.151 ns
sorted_o(58) <= unsorted_i(59); -- 2.153 ns
sorted_o(59) <= unsorted_i(58); -- 2.167 ns
sorted_o(60) <= unsorted_i(60); -- 2.175 ns
sorted_o(61) <= unsorted_i(61); -- 2.231 ns
sorted_o(62) <= unsorted_i(63); -- 2.233 ns
sorted_o(63) <= unsorted_i(62); -- 2.247 ns
sorted_o(64) <= unsorted_i(64); -- 2.255 ns
sorted_o(65) <= unsorted_i(65); -- 2.311 ns
sorted_o(66) <= unsorted_i(67); -- 2.313 ns
sorted_o(67) <= unsorted_i(66); -- 2.327 ns
sorted_o(68) <= unsorted_i(68); -- 2.335 ns
sorted_o(69) <= unsorted_i(69); -- 2.391 ns
sorted_o(70) <= unsorted_i(71); -- 2.393 ns
sorted_o(71) <= unsorted_i(70); -- 2.407 ns
sorted_o(72) <= unsorted_i(72); -- 2.417 ns
sorted_o(73) <= unsorted_i(73); -- 2.473 ns
sorted_o(74) <= unsorted_i(75); -- 2.475 ns
sorted_o(75) <= unsorted_i(74); -- 2.489 ns
sorted_o(76) <= unsorted_i(76); -- 2.498 ns
sorted_o(77) <= unsorted_i(77); -- 2.554 ns
sorted_o(78) <= unsorted_i(79); -- 2.556 ns
sorted_o(79) <= unsorted_i(78); -- 2.570 ns
sorted_o(80) <= unsorted_i(80); -- 2.580 ns
sorted_o(81) <= unsorted_i(81); -- 2.636 ns
sorted_o(82) <= unsorted_i(83); -- 2.638 ns
sorted_o(83) <= unsorted_i(82); -- 2.652 ns
sorted_o(84) <= unsorted_i(84); -- 2.661 ns
sorted_o(85) <= unsorted_i(85); -- 2.717 ns
sorted_o(86) <= unsorted_i(87); -- 2.719 ns
sorted_o(87) <= unsorted_i(86); -- 2.733 ns
sorted_o(88) <= unsorted_i(88); -- 2.819 ns
sorted_o(89) <= unsorted_i(89); -- 2.875 ns
sorted_o(90) <= unsorted_i(91); -- 2.877 ns
sorted_o(91) <= unsorted_i(90); -- 2.891 ns
sorted_o(92) <= unsorted_i(92); -- 2.896 ns
sorted_o(93) <= unsorted_i(93); -- 2.952 ns
sorted_o(94) <= unsorted_i(95); -- 2.954 ns
sorted_o(95) <= unsorted_i(94); -- 2.968 ns
sorted_o(96) <= unsorted_i(96); -- 2.972 ns
sorted_o(97) <= unsorted_i(97); -- 3.028 ns
sorted_o(98) <= unsorted_i(99); -- 3.030 ns
sorted_o(99) <= unsorted_i(98); -- 3.044 ns
sorted_o(100) <= unsorted_i(100); -- 3.049 ns
sorted_o(101) <= unsorted_i(101); -- 3.105 ns
sorted_o(102) <= unsorted_i(103); -- 3.107 ns
sorted_o(103) <= unsorted_i(102); -- 3.121 ns
sorted_o(104) <= unsorted_i(104); -- 3.125 ns
sorted_o(105) <= unsorted_i(105); -- 3.181 ns
sorted_o(106) <= unsorted_i(107); -- 3.183 ns
sorted_o(107) <= unsorted_i(106); -- 3.197 ns
sorted_o(108) <= unsorted_i(108); -- 3.203 ns
sorted_o(109) <= unsorted_i(109); -- 3.259 ns
sorted_o(110) <= unsorted_i(111); -- 3.261 ns
sorted_o(111) <= unsorted_i(110); -- 3.275 ns
sorted_o(112) <= unsorted_i(112); -- 3.281 ns
sorted_o(113) <= unsorted_i(113); -- 3.337 ns
sorted_o(114) <= unsorted_i(115); -- 3.339 ns
sorted_o(115) <= unsorted_i(114); -- 3.353 ns
sorted_o(116) <= unsorted_i(116); -- 3.359 ns
sorted_o(117) <= unsorted_i(117); -- 3.415 ns
sorted_o(118) <= unsorted_i(119); -- 3.417 ns
sorted_o(119) <= unsorted_i(118); -- 3.431 ns
sorted_o(120) <= unsorted_i(120); -- 3.441 ns
sorted_o(121) <= unsorted_i(121); -- 3.497 ns
sorted_o(122) <= unsorted_i(123); -- 3.499 ns
sorted_o(123) <= unsorted_i(122); -- 3.513 ns
sorted_o(124) <= unsorted_i(124); -- 3.521 ns
sorted_o(125) <= unsorted_i(125); -- 3.577 ns
sorted_o(126) <= unsorted_i(127); -- 3.579 ns
sorted_o(127) <= unsorted_i(126); -- 3.593 ns
sorted_o(128) <= unsorted_i(128); -- 3.601 ns
sorted_o(129) <= unsorted_i(129); -- 3.657 ns
sorted_o(130) <= unsorted_i(131); -- 3.659 ns
sorted_o(131) <= unsorted_i(130); -- 3.673 ns
sorted_o(132) <= unsorted_i(132); -- 3.681 ns
sorted_o(133) <= unsorted_i(133); -- 3.737 ns
sorted_o(134) <= unsorted_i(135); -- 3.739 ns
sorted_o(135) <= unsorted_i(134); -- 3.753 ns
sorted_o(136) <= unsorted_i(136); -- 3.762 ns
sorted_o(137) <= unsorted_i(137); -- 3.818 ns
sorted_o(138) <= unsorted_i(139); -- 3.820 ns
sorted_o(139) <= unsorted_i(138); -- 3.834 ns
sorted_o(140) <= unsorted_i(140); -- 3.844 ns
sorted_o(141) <= unsorted_i(141); -- 3.900 ns
sorted_o(142) <= unsorted_i(143); -- 3.902 ns
sorted_o(143) <= unsorted_i(142); -- 3.916 ns
sorted_o(144) <= unsorted_i(144); -- 3.926 ns
sorted_o(145) <= unsorted_i(145); -- 3.982 ns
sorted_o(146) <= unsorted_i(147); -- 3.984 ns
sorted_o(147) <= unsorted_i(146); -- 3.998 ns
sorted_o(148) <= unsorted_i(148); -- 4.007 ns
sorted_o(149) <= unsorted_i(149); -- 4.063 ns
sorted_o(150) <= unsorted_i(151); -- 4.065 ns
sorted_o(151) <= unsorted_i(150); -- 4.079 ns
sorted_o(152) <= unsorted_i(152); -- 4.165 ns
sorted_o(153) <= unsorted_i(153); -- 4.221 ns
sorted_o(154) <= unsorted_i(155); -- 4.223 ns
sorted_o(155) <= unsorted_i(154); -- 4.237 ns
sorted_o(156) <= unsorted_i(156); -- 4.242 ns
sorted_o(157) <= unsorted_i(157); -- 4.298 ns
sorted_o(158) <= unsorted_i(159); -- 4.300 ns
sorted_o(159) <= unsorted_i(158); -- 4.314 ns
sorted_o(160) <= unsorted_i(160); -- 4.318 ns
sorted_o(161) <= unsorted_i(161); -- 4.374 ns
sorted_o(162) <= unsorted_i(163); -- 4.376 ns
sorted_o(163) <= unsorted_i(162); -- 4.390 ns
sorted_o(164) <= unsorted_i(164); -- 4.394 ns
sorted_o(165) <= unsorted_i(165); -- 4.450 ns
sorted_o(166) <= unsorted_i(167); -- 4.452 ns
sorted_o(167) <= unsorted_i(166); -- 4.466 ns
sorted_o(168) <= unsorted_i(168); -- 4.471 ns
sorted_o(169) <= unsorted_i(169); -- 4.527 ns
sorted_o(170) <= unsorted_i(171); -- 4.529 ns
sorted_o(171) <= unsorted_i(170); -- 4.543 ns
sorted_o(172) <= unsorted_i(172); -- 4.549 ns
sorted_o(173) <= unsorted_i(173); -- 4.605 ns
sorted_o(174) <= unsorted_i(175); -- 4.607 ns
sorted_o(175) <= unsorted_i(174); -- 4.621 ns
sorted_o(176) <= unsorted_i(176); -- 4.627 ns
sorted_o(177) <= unsorted_i(177); -- 4.683 ns
sorted_o(178) <= unsorted_i(179); -- 4.685 ns
sorted_o(179) <= unsorted_i(178); -- 4.699 ns
sorted_o(180) <= unsorted_i(180); -- 4.705 ns
sorted_o(181) <= unsorted_i(184); -- 4.758 ns
sorted_o(182) <= unsorted_i(181); -- 4.761 ns
sorted_o(183) <= unsorted_i(183); -- 4.763 ns
sorted_o(184) <= unsorted_i(182); -- 4.777 ns
sorted_o(185) <= unsorted_i(185); -- 4.814 ns
sorted_o(186) <= unsorted_i(187); -- 4.816 ns
sorted_o(187) <= unsorted_i(186); -- 4.830 ns
sorted_o(188) <= unsorted_i(188); -- 4.838 ns
sorted_o(189) <= unsorted_i(189); -- 4.894 ns
sorted_o(190) <= unsorted_i(191); -- 4.896 ns
sorted_o(191) <= unsorted_i(190); -- 4.910 ns
sorted_o(192) <= unsorted_i(192); -- 4.918 ns
sorted_o(193) <= unsorted_i(193); -- 4.974 ns
sorted_o(194) <= unsorted_i(195); -- 4.976 ns
sorted_o(195) <= unsorted_i(194); -- 4.990 ns
sorted_o(196) <= unsorted_i(196); -- 4.998 ns
sorted_o(197) <= unsorted_i(197); -- 5.054 ns
sorted_o(198) <= unsorted_i(199); -- 5.056 ns
sorted_o(199) <= unsorted_i(198); -- 5.070 ns
sorted_o(200) <= unsorted_i(200); -- 5.079 ns
sorted_o(201) <= unsorted_i(201); -- 5.135 ns
sorted_o(202) <= unsorted_i(203); -- 5.137 ns
sorted_o(203) <= unsorted_i(202); -- 5.151 ns
sorted_o(204) <= unsorted_i(204); -- 5.161 ns
sorted_o(205) <= unsorted_i(205); -- 5.217 ns
sorted_o(206) <= unsorted_i(207); -- 5.219 ns
sorted_o(207) <= unsorted_i(206); -- 5.233 ns
sorted_o(208) <= unsorted_i(208); -- 5.243 ns
sorted_o(209) <= unsorted_i(209); -- 5.299 ns
sorted_o(210) <= unsorted_i(211); -- 5.301 ns
sorted_o(211) <= unsorted_i(210); -- 5.315 ns
sorted_o(212) <= unsorted_i(212); -- 5.324 ns
sorted_o(213) <= unsorted_i(213); -- 5.380 ns
sorted_o(214) <= unsorted_i(215); -- 5.382 ns
sorted_o(215) <= unsorted_i(214); -- 5.396 ns
sorted_o(216) <= unsorted_i(216); -- 5.482 ns
sorted_o(217) <= unsorted_i(217); -- 5.538 ns
sorted_o(218) <= unsorted_i(219); -- 5.540 ns
sorted_o(219) <= unsorted_i(218); -- 5.554 ns
sorted_o(220) <= unsorted_i(220); -- 5.559 ns
sorted_o(221) <= unsorted_i(221); -- 5.615 ns
sorted_o(222) <= unsorted_i(223); -- 5.617 ns
sorted_o(223) <= unsorted_i(222); -- 5.631 ns
sorted_o(224) <= unsorted_i(224); -- 5.635 ns
sorted_o(225) <= unsorted_i(225); -- 5.691 ns
sorted_o(226) <= unsorted_i(227); -- 5.693 ns
sorted_o(227) <= unsorted_i(226); -- 5.707 ns
sorted_o(228) <= unsorted_i(228); -- 5.711 ns
sorted_o(229) <= unsorted_i(229); -- 5.767 ns
sorted_o(230) <= unsorted_i(231); -- 5.769 ns
sorted_o(231) <= unsorted_i(230); -- 5.783 ns
sorted_o(232) <= unsorted_i(232); -- 5.788 ns
sorted_o(233) <= unsorted_i(233); -- 5.844 ns
sorted_o(234) <= unsorted_i(235); -- 5.846 ns
sorted_o(235) <= unsorted_i(234); -- 5.860 ns
sorted_o(236) <= unsorted_i(236); -- 5.866 ns
sorted_o(237) <= unsorted_i(237); -- 5.922 ns
sorted_o(238) <= unsorted_i(239); -- 5.924 ns
sorted_o(239) <= unsorted_i(238); -- 5.938 ns
sorted_o(240) <= unsorted_i(240); -- 5.944 ns
sorted_o(241) <= unsorted_i(241); -- 6.000 ns
sorted_o(242) <= unsorted_i(243); -- 6.002 ns
sorted_o(243) <= unsorted_i(242); -- 6.016 ns
sorted_o(244) <= unsorted_i(244); -- 6.022 ns
sorted_o(245) <= unsorted_i(245); -- 6.078 ns
sorted_o(246) <= unsorted_i(247); -- 6.080 ns
sorted_o(247) <= unsorted_i(246); -- 6.094 ns
sorted_o(248) <= unsorted_i(248); -- 6.206 ns
sorted_o(249) <= unsorted_i(249); -- 6.262 ns
sorted_o(250) <= unsorted_i(251); -- 6.264 ns
sorted_o(251) <= unsorted_i(250); -- 6.278 ns
sorted_o(252) <= unsorted_i(252); -- 6.286 ns
sorted_o(253) <= unsorted_i(253); -- 6.342 ns
sorted_o(254) <= unsorted_i(255); -- 6.344 ns
sorted_o(255) <= unsorted_i(254); -- 6.358 ns
sorted_o(256) <= unsorted_i(256); -- 6.366 ns
sorted_o(257) <= unsorted_i(257); -- 6.422 ns
sorted_o(258) <= unsorted_i(259); -- 6.424 ns
sorted_o(259) <= unsorted_i(258); -- 6.438 ns
sorted_o(260) <= unsorted_i(260); -- 6.446 ns
sorted_o(261) <= unsorted_i(261); -- 6.502 ns
sorted_o(262) <= unsorted_i(263); -- 6.504 ns
sorted_o(263) <= unsorted_i(262); -- 6.518 ns
sorted_o(264) <= unsorted_i(264); -- 6.527 ns
sorted_o(265) <= unsorted_i(265); -- 6.583 ns
sorted_o(266) <= unsorted_i(267); -- 6.585 ns
sorted_o(267) <= unsorted_i(266); -- 6.599 ns
sorted_o(268) <= unsorted_i(268); -- 6.609 ns
sorted_o(269) <= unsorted_i(269); -- 6.665 ns
sorted_o(270) <= unsorted_i(271); -- 6.667 ns
sorted_o(271) <= unsorted_i(270); -- 6.681 ns
sorted_o(272) <= unsorted_i(272); -- 6.691 ns
sorted_o(273) <= unsorted_i(273); -- 6.747 ns
sorted_o(274) <= unsorted_i(275); -- 6.749 ns
sorted_o(275) <= unsorted_i(274); -- 6.763 ns
sorted_o(276) <= unsorted_i(276); -- 6.772 ns
sorted_o(277) <= unsorted_i(277); -- 6.828 ns
sorted_o(278) <= unsorted_i(279); -- 6.830 ns
sorted_o(279) <= unsorted_i(278); -- 6.844 ns
sorted_o(280) <= unsorted_i(280); -- 6.930 ns
sorted_o(281) <= unsorted_i(281); -- 6.986 ns
sorted_o(282) <= unsorted_i(283); -- 6.988 ns
sorted_o(283) <= unsorted_i(282); -- 7.002 ns
sorted_o(284) <= unsorted_i(284); -- 7.007 ns
sorted_o(285) <= unsorted_i(285); -- 7.063 ns
sorted_o(286) <= unsorted_i(287); -- 7.065 ns
sorted_o(287) <= unsorted_i(286); -- 7.079 ns
sorted_o(288) <= unsorted_i(288); -- 7.083 ns
sorted_o(289) <= unsorted_i(289); -- 7.139 ns
sorted_o(290) <= unsorted_i(291); -- 7.141 ns
sorted_o(291) <= unsorted_i(290); -- 7.155 ns
sorted_o(292) <= unsorted_i(292); -- 7.159 ns
sorted_o(293) <= unsorted_i(293); -- 7.215 ns
sorted_o(294) <= unsorted_i(295); -- 7.217 ns
sorted_o(295) <= unsorted_i(294); -- 7.231 ns
sorted_o(296) <= unsorted_i(296); -- 7.236 ns
sorted_o(297) <= unsorted_i(297); -- 7.292 ns
sorted_o(298) <= unsorted_i(299); -- 7.294 ns
sorted_o(299) <= unsorted_i(298); -- 7.308 ns
sorted_o(300) <= unsorted_i(300); -- 7.314 ns
sorted_o(301) <= unsorted_i(301); -- 7.370 ns
sorted_o(302) <= unsorted_i(303); -- 7.372 ns
sorted_o(303) <= unsorted_i(302); -- 7.386 ns
sorted_o(304) <= unsorted_i(304); -- 7.392 ns
sorted_o(305) <= unsorted_i(305); -- 7.448 ns
sorted_o(306) <= unsorted_i(307); -- 7.450 ns
sorted_o(307) <= unsorted_i(306); -- 7.464 ns
sorted_o(308) <= unsorted_i(308); -- 7.470 ns
sorted_o(309) <= unsorted_i(309); -- 7.526 ns
sorted_o(310) <= unsorted_i(311); -- 7.528 ns
sorted_o(311) <= unsorted_i(310); -- 7.542 ns
sorted_o(312) <= unsorted_i(312); -- 7.575 ns
sorted_o(313) <= unsorted_i(313); -- 7.631 ns
sorted_o(314) <= unsorted_i(315); -- 7.633 ns
sorted_o(315) <= unsorted_i(314); -- 7.647 ns
sorted_o(316) <= unsorted_i(316); -- 7.655 ns
sorted_o(317) <= unsorted_i(317); -- 7.711 ns
sorted_o(318) <= unsorted_i(319); -- 7.713 ns
sorted_o(319) <= unsorted_i(318); -- 7.727 ns
sorted_o(320) <= unsorted_i(320); -- 7.735 ns
sorted_o(321) <= unsorted_i(321); -- 7.791 ns
sorted_o(322) <= unsorted_i(323); -- 7.793 ns
sorted_o(323) <= unsorted_i(322); -- 7.807 ns
sorted_o(324) <= unsorted_i(324); -- 7.815 ns
sorted_o(325) <= unsorted_i(325); -- 7.871 ns
sorted_o(326) <= unsorted_i(327); -- 7.873 ns
sorted_o(327) <= unsorted_i(326); -- 7.887 ns
sorted_o(328) <= unsorted_i(328); -- 7.896 ns
sorted_o(329) <= unsorted_i(329); -- 7.952 ns
sorted_o(330) <= unsorted_i(331); -- 7.954 ns
sorted_o(331) <= unsorted_i(330); -- 7.968 ns
sorted_o(332) <= unsorted_i(332); -- 7.978 ns
sorted_o(333) <= unsorted_i(333); -- 8.034 ns
sorted_o(334) <= unsorted_i(335); -- 8.036 ns
sorted_o(335) <= unsorted_i(334); -- 8.050 ns
sorted_o(336) <= unsorted_i(336); -- 8.060 ns
sorted_o(337) <= unsorted_i(337); -- 8.116 ns
sorted_o(338) <= unsorted_i(339); -- 8.118 ns
sorted_o(339) <= unsorted_i(338); -- 8.132 ns
sorted_o(340) <= unsorted_i(340); -- 8.141 ns
sorted_o(341) <= unsorted_i(341); -- 8.197 ns
sorted_o(342) <= unsorted_i(343); -- 8.199 ns
sorted_o(343) <= unsorted_i(342); -- 8.213 ns
sorted_o(344) <= unsorted_i(344); -- 8.299 ns
sorted_o(345) <= unsorted_i(345); -- 8.355 ns
sorted_o(346) <= unsorted_i(347); -- 8.357 ns
sorted_o(347) <= unsorted_i(346); -- 8.371 ns
sorted_o(348) <= unsorted_i(348); -- 8.376 ns
sorted_o(349) <= unsorted_i(349); -- 8.432 ns
sorted_o(350) <= unsorted_i(351); -- 8.434 ns
sorted_o(351) <= unsorted_i(350); -- 8.448 ns
sorted_o(352) <= unsorted_i(352); -- 8.452 ns
sorted_o(353) <= unsorted_i(353); -- 8.508 ns
sorted_o(354) <= unsorted_i(355); -- 8.510 ns
sorted_o(355) <= unsorted_i(354); -- 8.524 ns
sorted_o(356) <= unsorted_i(356); -- 8.528 ns
sorted_o(357) <= unsorted_i(357); -- 8.584 ns
sorted_o(358) <= unsorted_i(359); -- 8.586 ns
sorted_o(359) <= unsorted_i(358); -- 8.600 ns
sorted_o(360) <= unsorted_i(360); -- 8.605 ns
sorted_o(361) <= unsorted_i(361); -- 8.661 ns
sorted_o(362) <= unsorted_i(363); -- 8.663 ns
sorted_o(363) <= unsorted_i(362); -- 8.677 ns
sorted_o(364) <= unsorted_i(364); -- 8.683 ns
sorted_o(365) <= unsorted_i(365); -- 8.739 ns
sorted_o(366) <= unsorted_i(367); -- 8.741 ns
sorted_o(367) <= unsorted_i(366); -- 8.755 ns
sorted_o(368) <= unsorted_i(368); -- 8.761 ns
sorted_o(369) <= unsorted_i(369); -- 8.817 ns
sorted_o(370) <= unsorted_i(371); -- 8.819 ns
sorted_o(371) <= unsorted_i(370); -- 8.833 ns
sorted_o(372) <= unsorted_i(372); -- 8.839 ns
sorted_o(373) <= unsorted_i(373); -- 8.895 ns
sorted_o(374) <= unsorted_i(375); -- 8.897 ns
sorted_o(375) <= unsorted_i(374); -- 8.911 ns
sorted_o(376) <= unsorted_i(376); -- 8.931 ns
sorted_o(377) <= unsorted_i(377); -- 8.987 ns
sorted_o(378) <= unsorted_i(379); -- 8.989 ns
sorted_o(379) <= unsorted_i(378); -- 9.003 ns
sorted_o(380) <= unsorted_i(380); -- 9.010 ns
sorted_o(381) <= unsorted_i(381); -- 9.066 ns
sorted_o(382) <= unsorted_i(383); -- 9.068 ns
sorted_o(383) <= unsorted_i(382); -- 9.082 ns
sorted_o(384) <= unsorted_i(384); -- 9.090 ns
sorted_o(385) <= unsorted_i(385); -- 9.146 ns
sorted_o(386) <= unsorted_i(387); -- 9.148 ns
sorted_o(387) <= unsorted_i(386); -- 9.162 ns
sorted_o(388) <= unsorted_i(388); -- 9.171 ns
sorted_o(389) <= unsorted_i(389); -- 9.227 ns
sorted_o(390) <= unsorted_i(391); -- 9.229 ns
sorted_o(391) <= unsorted_i(390); -- 9.243 ns
sorted_o(392) <= unsorted_i(392); -- 9.252 ns
sorted_o(393) <= unsorted_i(393); -- 9.308 ns
sorted_o(394) <= unsorted_i(395); -- 9.310 ns
sorted_o(395) <= unsorted_i(394); -- 9.324 ns
sorted_o(396) <= unsorted_i(396); -- 9.334 ns
sorted_o(397) <= unsorted_i(397); -- 9.390 ns
sorted_o(398) <= unsorted_i(399); -- 9.392 ns
sorted_o(399) <= unsorted_i(398); -- 9.406 ns
sorted_o(400) <= unsorted_i(400); -- 9.415 ns
sorted_o(401) <= unsorted_i(401); -- 9.471 ns
sorted_o(402) <= unsorted_i(403); -- 9.473 ns
sorted_o(403) <= unsorted_i(402); -- 9.487 ns
sorted_o(404) <= unsorted_i(404); -- 9.497 ns
sorted_o(405) <= unsorted_i(405); -- 9.553 ns
sorted_o(406) <= unsorted_i(407); -- 9.555 ns
sorted_o(407) <= unsorted_i(406); -- 9.569 ns
sorted_o(408) <= unsorted_i(408); -- 9.655 ns
sorted_o(409) <= unsorted_i(409); -- 9.711 ns
sorted_o(410) <= unsorted_i(411); -- 9.713 ns
sorted_o(411) <= unsorted_i(410); -- 9.727 ns
sorted_o(412) <= unsorted_i(412); -- 9.731 ns
sorted_o(413) <= unsorted_i(413); -- 9.787 ns
sorted_o(414) <= unsorted_i(415); -- 9.789 ns
sorted_o(415) <= unsorted_i(414); -- 9.803 ns
sorted_o(416) <= unsorted_i(416); -- 9.808 ns
sorted_o(417) <= unsorted_i(417); -- 9.864 ns
sorted_o(418) <= unsorted_i(419); -- 9.866 ns
sorted_o(419) <= unsorted_i(418); -- 9.880 ns
sorted_o(420) <= unsorted_i(420); -- 9.884 ns
sorted_o(421) <= unsorted_i(421); -- 9.940 ns
sorted_o(422) <= unsorted_i(423); -- 9.942 ns
sorted_o(423) <= unsorted_i(422); -- 9.956 ns
sorted_o(424) <= unsorted_i(424); -- 9.961 ns
sorted_o(425) <= unsorted_i(425); -- 10.017 ns
sorted_o(426) <= unsorted_i(427); -- 10.019 ns
sorted_o(427) <= unsorted_i(426); -- 10.033 ns
sorted_o(428) <= unsorted_i(428); -- 10.038 ns
sorted_o(429) <= unsorted_i(429); -- 10.094 ns
sorted_o(430) <= unsorted_i(431); -- 10.096 ns
sorted_o(431) <= unsorted_i(430); -- 10.110 ns
sorted_o(432) <= unsorted_i(432); -- 10.116 ns
sorted_o(433) <= unsorted_i(433); -- 10.172 ns
sorted_o(434) <= unsorted_i(435); -- 10.174 ns
sorted_o(435) <= unsorted_i(434); -- 10.188 ns
sorted_o(436) <= unsorted_i(436); -- 10.195 ns
sorted_o(437) <= unsorted_i(440); -- 10.246 ns
sorted_o(438) <= unsorted_i(437); -- 10.251 ns
sorted_o(439) <= unsorted_i(439); -- 10.253 ns
sorted_o(440) <= unsorted_i(438); -- 10.267 ns
sorted_o(441) <= unsorted_i(441); -- 10.302 ns
sorted_o(442) <= unsorted_i(443); -- 10.304 ns
sorted_o(443) <= unsorted_i(442); -- 10.318 ns
sorted_o(444) <= unsorted_i(444); -- 10.325 ns
sorted_o(445) <= unsorted_i(445); -- 10.381 ns
sorted_o(446) <= unsorted_i(447); -- 10.383 ns
sorted_o(447) <= unsorted_i(446); -- 10.397 ns
sorted_o(448) <= unsorted_i(448); -- 10.405 ns
sorted_o(449) <= unsorted_i(449); -- 10.461 ns
sorted_o(450) <= unsorted_i(451); -- 10.463 ns
sorted_o(451) <= unsorted_i(450); -- 10.477 ns
sorted_o(452) <= unsorted_i(452); -- 10.486 ns
sorted_o(453) <= unsorted_i(453); -- 10.542 ns
sorted_o(454) <= unsorted_i(455); -- 10.544 ns
sorted_o(455) <= unsorted_i(454); -- 10.558 ns
sorted_o(456) <= unsorted_i(456); -- 10.567 ns
sorted_o(457) <= unsorted_i(457); -- 10.623 ns
sorted_o(458) <= unsorted_i(459); -- 10.625 ns
sorted_o(459) <= unsorted_i(458); -- 10.639 ns
sorted_o(460) <= unsorted_i(460); -- 10.649 ns
sorted_o(461) <= unsorted_i(461); -- 10.705 ns
sorted_o(462) <= unsorted_i(463); -- 10.707 ns
sorted_o(463) <= unsorted_i(462); -- 10.721 ns
sorted_o(464) <= unsorted_i(464); -- 10.731 ns
sorted_o(465) <= unsorted_i(465); -- 10.787 ns
sorted_o(466) <= unsorted_i(467); -- 10.789 ns
sorted_o(467) <= unsorted_i(466); -- 10.803 ns
sorted_o(468) <= unsorted_i(468); -- 10.812 ns
sorted_o(469) <= unsorted_i(469); -- 10.868 ns
sorted_o(470) <= unsorted_i(471); -- 10.870 ns
sorted_o(471) <= unsorted_i(470); -- 10.884 ns
sorted_o(472) <= unsorted_i(472); -- 10.970 ns
sorted_o(473) <= unsorted_i(473); -- 11.026 ns
sorted_o(474) <= unsorted_i(475); -- 11.028 ns
sorted_o(475) <= unsorted_i(474); -- 11.042 ns
sorted_o(476) <= unsorted_i(476); -- 11.047 ns
sorted_o(477) <= unsorted_i(477); -- 11.103 ns
sorted_o(478) <= unsorted_i(479); -- 11.105 ns
sorted_o(479) <= unsorted_i(478); -- 11.119 ns
sorted_o(480) <= unsorted_i(480); -- 11.123 ns
sorted_o(481) <= unsorted_i(481); -- 11.179 ns
sorted_o(482) <= unsorted_i(483); -- 11.181 ns
sorted_o(483) <= unsorted_i(482); -- 11.195 ns
sorted_o(484) <= unsorted_i(484); -- 11.199 ns
sorted_o(485) <= unsorted_i(485); -- 11.255 ns
sorted_o(486) <= unsorted_i(487); -- 11.257 ns
sorted_o(487) <= unsorted_i(486); -- 11.271 ns
sorted_o(488) <= unsorted_i(488); -- 11.276 ns
sorted_o(489) <= unsorted_i(489); -- 11.332 ns
sorted_o(490) <= unsorted_i(491); -- 11.334 ns
sorted_o(491) <= unsorted_i(490); -- 11.348 ns
sorted_o(492) <= unsorted_i(492); -- 11.354 ns
sorted_o(493) <= unsorted_i(493); -- 11.410 ns
sorted_o(494) <= unsorted_i(495); -- 11.412 ns
sorted_o(495) <= unsorted_i(494); -- 11.426 ns
end architecture;
core/tdc_package.vhd deleted 100644 → 0
View file @ c9d9b7d6
-------------------------------------------------------------------------------
-- TDC Core / CERN
-------------------------------------------------------------------------------
--
-- unit name: tdc_package
--
-- author: Sebastien Bourdeauducq, sebastien@milkymist.org
--
-- description: Component declarations for the TDC core
--
-- references: http://www.ohwr.org/projects/tdc-core
--
-------------------------------------------------------------------------------
-- last changes:
-- 2011-11-07 SB Pre-inversion
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-10-25 SB Added single/multi channel bank components
-- 2011-08-03 SB Created file
-------------------------------------------------------------------------------
-- Copyright (C) 2011 CERN
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, version 3 of the License.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- DESCRIPTION:
-- This contains component declarations for all the modules of the TDC core.
-- It is used both internally to instantiate modules, and by the user to
-- instantiate the top-level "tdc" module.
library ieee;
use ieee.std_logic_1164.all;
package tdc_package is
component tdc is
generic(
g_CHANNEL_COUNT : positive := 2;
g_CARRY4_COUNT : positive := 100;
g_RAW_COUNT : positive := 9;
g_FP_COUNT : positive := 13;
g_EXHIS_COUNT : positive := 4;
g_COARSE_COUNT : positive := 25;
g_RO_LENGTH : positive := 20;
g_FCOUNTER_WIDTH : positive := 13;
g_FTIMER_WIDTH : positive := 10
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
ready_o : out std_logic;
cc_rst_i : in std_logic;
cc_cy_o : out std_logic;
deskew_i : in std_logic_vector(g_CHANNEL_COUNT*(g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
signal_i : in std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
calib_i : in std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
detect_o : out std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
polarity_o : out std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
raw_o : out std_logic_vector(g_CHANNEL_COUNT*g_RAW_COUNT-1 downto 0);
fp_o : out std_logic_vector(g_CHANNEL_COUNT*(g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
freeze_req_i : in std_logic;
freeze_ack_o : out std_logic;
cs_next_i : in std_logic;
cs_last_o : out std_logic;
calib_sel_i : in std_logic;
lut_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
lut_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0);
his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
oc_start_i : in std_logic;
oc_ready_o : out std_logic;
oc_freq_o : out std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
oc_sfreq_o : out std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0)
);
end component;
component tdc_controller is
generic(
g_RAW_COUNT : positive;
g_FP_COUNT : positive;
g_EXHIS_COUNT : positive;
g_FCOUNTER_WIDTH : positive
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
ready_o : out std_logic;
next_o : out std_logic;
last_i : in std_logic;
calib_sel_o : out std_logic;
lut_a_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
lut_we_o : out std_logic;
lut_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0);
c_detect_i : in std_logic;
c_raw_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_a_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
his_we_o : out std_logic;
his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
his_d_i : in std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
oc_start_o : out std_logic;
oc_ready_i : in std_logic;
oc_freq_i : in std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
oc_store_o : out std_logic;
oc_sfreq_i : in std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
freeze_req_i : in std_logic;
freeze_ack_o : out std_logic
);
end component;
component tdc_channelbank is
generic(
g_CHANNEL_COUNT : positive;
g_CARRY4_COUNT : positive;
g_RAW_COUNT : positive;
g_FP_COUNT : positive;
g_EXHIS_COUNT : positive;
g_COARSE_COUNT : positive;
g_RO_LENGTH : positive;
g_FCOUNTER_WIDTH : positive;
g_FTIMER_WIDTH : positive
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
cc_rst_i : in std_logic;
cc_cy_o : out std_logic;
next_i : in std_logic;
last_o : out std_logic;
calib_sel_i : in std_logic;
deskew_i : in std_logic_vector(g_CHANNEL_COUNT*(g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
signal_i : in std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
calib_i : in std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
detect_o : out std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
polarity_o : out std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
raw_o : out std_logic_vector(g_CHANNEL_COUNT*g_RAW_COUNT-1 downto 0);
fp_o : out std_logic_vector(g_CHANNEL_COUNT*(g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
lut_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
lut_we_i : in std_logic;
lut_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0);
lut_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0);
c_detect_o : out std_logic;
c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_we_i : in std_logic;
his_d_i : in std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
oc_start_i : in std_logic;
oc_ready_o : out std_logic;
oc_freq_o : out std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
oc_store_i : in std_logic;
oc_sfreq_o : out std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0)
);
end component;
component tdc_channelbank_single is
generic(
g_CARRY4_COUNT : positive;
g_RAW_COUNT : positive;
g_FP_COUNT : positive;
g_EXHIS_COUNT : positive;
g_COARSE_COUNT : positive;
g_RO_LENGTH : positive;
g_FCOUNTER_WIDTH : positive;
g_FTIMER_WIDTH : positive
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
cc_rst_i : in std_logic;
cc_cy_o : out std_logic;
next_i : in std_logic;
last_o : out std_logic;
calib_sel_i : in std_logic;
deskew_i : in std_logic_vector(g_COARSE_COUNT+g_FP_COUNT-1 downto 0);
signal_i : in std_logic;
calib_i : in std_logic;
detect_o : out std_logic;
polarity_o : out std_logic;
raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
fp_o : out std_logic_vector(g_COARSE_COUNT+g_FP_COUNT-1 downto 0);
lut_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
lut_we_i : in std_logic;
lut_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0);
lut_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0);
c_detect_o : out std_logic;
c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_we_i : in std_logic;
his_d_i : in std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
oc_start_i : in std_logic;
oc_ready_o : out std_logic;
oc_freq_o : out std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
oc_store_i : in std_logic;
oc_sfreq_o : out std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0)
);
end component;
component tdc_channelbank_multi is
generic(
g_CHANNEL_COUNT : positive;
g_CARRY4_COUNT : positive;
g_RAW_COUNT : positive;
g_FP_COUNT : positive;
g_EXHIS_COUNT : positive;
g_COARSE_COUNT : positive;
g_RO_LENGTH : positive;
g_FCOUNTER_WIDTH : positive;
g_FTIMER_WIDTH : positive
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
cc_rst_i : in std_logic;
cc_cy_o : out std_logic;
next_i : in std_logic;
last_o : out std_logic;
calib_sel_i : in std_logic;
deskew_i : in std_logic_vector(g_CHANNEL_COUNT*(g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
signal_i : in std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
calib_i : in std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
detect_o : out std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
polarity_o : out std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
raw_o : out std_logic_vector(g_CHANNEL_COUNT*g_RAW_COUNT-1 downto 0);
fp_o : out std_logic_vector(g_CHANNEL_COUNT*(g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
lut_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
lut_we_i : in std_logic;
lut_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0);
lut_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0);
c_detect_o : out std_logic;
c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_we_i : in std_logic;
his_d_i : in std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
oc_start_i : in std_logic;
oc_ready_o : out std_logic;
oc_freq_o : out std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
oc_store_i : in std_logic;
oc_sfreq_o : out std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0)
);
end component;
component tdc_freqc is
generic(
g_COUNTER_WIDTH : positive;
g_TIMER_WIDTH : positive
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
clk_m_i : in std_logic;
start_i : in std_logic;
ready_o : out std_logic;
freq_o : out std_logic_vector(g_COUNTER_WIDTH-1 downto 0)
);
end component;
component tdc_channel is
generic(
g_CARRY4_COUNT : positive;
g_RAW_COUNT : positive;
g_FP_COUNT : positive;
g_COARSE_COUNT : positive;
g_RO_LENGTH : positive
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
coarse_i : in std_logic_vector(g_COARSE_COUNT-1 downto 0);
deskew_i : in std_logic_vector((g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
signal_i : in std_logic;
calib_i : in std_logic;
calib_sel_i : in std_logic;
detect_o : out std_logic;
polarity_o : out std_logic;
raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
fp_o : out std_logic_vector((g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
lut_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
lut_we_i : in std_logic;
lut_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0);
lut_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0);
ro_en_i : in std_logic;
ro_clk_o : out std_logic
);
end component;
component tdc_ringosc is
generic(
g_LENGTH: positive
);
port(
en_i : in std_logic;
clk_o : out std_logic
);
end component;
component tdc_lbc is
generic(
g_N : positive;
g_NIN : positive;
g_IGNORE : natural
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
d_i : in std_logic_vector(g_NIN-1 downto 0);
ipolarity_o : out std_logic;
polarity_o : out std_logic;
count_o : out std_logic_vector(g_N-1 downto 0)
);
end component;
component tdc_delayline is
generic(
g_WIDTH: positive
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
signal_i : in std_logic;
taps_o : out std_logic_vector(4*g_WIDTH-1 downto 0)
);
end component;
component tdc_ordertaps is
generic(
g_WIDTH: positive
);
port(
unsorted_i : in std_logic_vector(4*g_WIDTH-1 downto 0);
sorted_o : out std_logic_vector(4*g_WIDTH-1 downto 0)
);
end component;
component tdc_divider is
generic(
g_WIDTH: positive
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
start_i : in std_logic;
dividend_i : in std_logic_vector(g_WIDTH-1 downto 0);
divisor_i : in std_logic_vector(g_WIDTH-1 downto 0);
ready_o : out std_logic;
quotient_o : out std_logic_vector(g_WIDTH-1 downto 0);
remainder_o : out std_logic_vector(g_WIDTH-1 downto 0)
);
end component;
component tdc_psync is
port(
clk_src_i : in std_logic;
p_i : in std_logic;
clk_dst_i : in std_logic;
p_o : out std_logic
);
end component;
end package;
hostif/Manifest.py deleted 100644 → 0
View file @ c9d9b7d6
modules = { "local" : [ "../core" ] }
files = [ "tdc_hostif_package.vhd", "tdc_hostif.vhd", "tdc_wb.vhd" ]
hostif/tdc_hostif.vhd deleted 100644 → 0
View file @ c9d9b7d6
-------------------------------------------------------------------------------
-- TDC Core / CERN
-------------------------------------------------------------------------------
--
-- unit name: tdc_hostif
--
-- author: Sebastien Bourdeauducq, sebastien@milkymist.org
--
-- description: Host interface for the TDC core
--
-- references: http://www.ohwr.org/projects/tdc-core
--
-------------------------------------------------------------------------------
-- last changes:
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-08-27 SB Reduced supported channel count to 8
-- 2011-08-26 SB Created file
-------------------------------------------------------------------------------
-- Copyright (C) 2011 CERN
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, version 3 of the License.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- DESCRIPTION:
-- Top level module of the TDC core, contains all logic including the optional
-- host interface. It instantiates the basic TDC core and a Wishbone interface.
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tdc_package.all;
use work.tdc_hostif_package.all;
entity tdc_hostif is
generic(
g_CHANNEL_COUNT : positive := 1;
g_CARRY4_COUNT : positive := 124;
g_RAW_COUNT : positive := 9;
g_FP_COUNT : positive := 13;
g_EXHIS_COUNT : positive := 4;
g_COARSE_COUNT : positive := 25;
g_RO_LENGTH : positive := 31;
g_FCOUNTER_WIDTH : positive := 13;
g_FTIMER_WIDTH : positive := 14
);
port(
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic;
cc_rst_i : in std_logic;
cc_cy_o : out std_logic;
signal_i : in std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
calib_i : in std_logic_vector(g_CHANNEL_COUNT-1 downto 0)
);
end entity;
architecture rtl of tdc_hostif is
signal reset : std_logic;
signal ready : std_logic;
signal cc_cy : std_logic;
signal deskew : std_logic_vector(g_CHANNEL_COUNT*(g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
signal detect : std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
signal polarity : std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
signal raw : std_logic_vector(g_CHANNEL_COUNT*g_RAW_COUNT-1 downto 0);
signal fp : std_logic_vector(g_CHANNEL_COUNT*(g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
signal freeze_req : std_logic;
signal freeze_ack : std_logic;
signal cs_next : std_logic;
signal cs_last : std_logic;
signal calib_sel : std_logic;
signal lut_a : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal lut_d : std_logic_vector(g_FP_COUNT-1 downto 0);
signal his_a : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal his_d : std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
signal oc_start : std_logic;
signal oc_ready : std_logic;
signal oc_freq : std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
signal oc_sfreq : std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
signal wbg_luta : std_logic_vector(15 downto 0);
signal wbg_lutd : std_logic_vector(31 downto 0);
signal wbg_hisa : std_logic_vector(15 downto 0);
signal wbg_hisd : std_logic_vector(31 downto 0);
signal wbg_fcr : std_logic_vector(31 downto 0);
signal wbg_fcsr : std_logic_vector(31 downto 0);
-- maximum number of channels the host interface can support
constant c_NCHAN: positive := 8;
signal wbg_des : std_logic_vector(c_NCHAN*64-1 downto 0);
signal wbg_pol : std_logic_vector(c_NCHAN-1 downto 0);
signal wbg_raw : std_logic_vector(c_NCHAN*32-1 downto 0);
signal wbg_mes : std_logic_vector(c_NCHAN*64-1 downto 0);
signal wbg_ie : std_logic_vector(c_NCHAN-1 downto 0);
begin
cmp_tdc: tdc
generic map(
g_CHANNEL_COUNT => g_CHANNEL_COUNT,
g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT,
g_FP_COUNT => g_FP_COUNT,
g_EXHIS_COUNT => g_EXHIS_COUNT,
g_COARSE_COUNT => g_COARSE_COUNT,
g_RO_LENGTH => g_RO_LENGTH,
g_FCOUNTER_WIDTH => g_FCOUNTER_WIDTH,
g_FTIMER_WIDTH => g_FTIMER_WIDTH
)
port map(
clk_i => wb_clk_i,
reset_i => reset,
ready_o => ready,
cc_rst_i => cc_rst_i,
cc_cy_o => cc_cy,
deskew_i => deskew,
signal_i => signal_i,
calib_i => calib_i,
detect_o => detect,
polarity_o => polarity,
raw_o => raw,
fp_o => fp,
freeze_req_i => freeze_req,
freeze_ack_o => freeze_ack,
cs_next_i => cs_next,
cs_last_o => cs_last,
calib_sel_i => calib_sel,
lut_a_i => lut_a,
lut_d_o => lut_d,
his_a_i => his_a,
his_d_o => his_d,
oc_start_i => oc_start,
oc_ready_o => oc_ready,
oc_freq_o => oc_freq,
oc_sfreq_o => oc_sfreq
);
cc_cy_o <= cc_cy;
cmp_wb: tdc_wb
port map(
rst_n_i => rst_n_i,
wb_clk_i => wb_clk_i,
wb_addr_i => wb_addr_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_irq_o => wb_irq_o,
tdc_cs_rst_o => reset,
tdc_cs_rdy_i => ready,
irq_isc_i => ready,
irq_icc_i => cc_cy,
tdc_dctl_req_o => freeze_req,
tdc_dctl_ack_i => freeze_ack,
tdc_csel_next_o => cs_next,
tdc_csel_last_i => cs_last,
tdc_cal_o => calib_sel,
tdc_fcc_st_o => oc_start,
tdc_fcc_rdy_i => oc_ready,
tdc_luta_o => wbg_luta,
tdc_lutd_i => wbg_lutd,
tdc_hisa_o => wbg_hisa,
tdc_hisd_i => wbg_hisd,
tdc_fcr_i => wbg_fcr,
tdc_fcsr_i => wbg_fcsr,
tdc_pol_i => wbg_pol,
-- begin autogenerated connections
tdc_desh0_o => wbg_des(63 downto 32),
tdc_desl0_o => wbg_des(31 downto 0),
tdc_desh1_o => wbg_des(127 downto 96),
tdc_desl1_o => wbg_des(95 downto 64),
tdc_desh2_o => wbg_des(191 downto 160),
tdc_desl2_o => wbg_des(159 downto 128),
tdc_desh3_o => wbg_des(255 downto 224),
tdc_desl3_o => wbg_des(223 downto 192),
tdc_desh4_o => wbg_des(319 downto 288),
tdc_desl4_o => wbg_des(287 downto 256),
tdc_desh5_o => wbg_des(383 downto 352),
tdc_desl5_o => wbg_des(351 downto 320),
tdc_desh6_o => wbg_des(447 downto 416),
tdc_desl6_o => wbg_des(415 downto 384),
tdc_desh7_o => wbg_des(511 downto 480),
tdc_desl7_o => wbg_des(479 downto 448),
tdc_raw0_i => wbg_raw(31 downto 0),
tdc_mesh0_i => wbg_mes(63 downto 32),
tdc_mesl0_i => wbg_mes(31 downto 0),
tdc_raw1_i => wbg_raw(63 downto 32),
tdc_mesh1_i => wbg_mes(127 downto 96),
tdc_mesl1_i => wbg_mes(95 downto 64),
tdc_raw2_i => wbg_raw(95 downto 64),
tdc_mesh2_i => wbg_mes(191 downto 160),
tdc_mesl2_i => wbg_mes(159 downto 128),
tdc_raw3_i => wbg_raw(127 downto 96),
tdc_mesh3_i => wbg_mes(255 downto 224),
tdc_mesl3_i => wbg_mes(223 downto 192),
tdc_raw4_i => wbg_raw(159 downto 128),
tdc_mesh4_i => wbg_mes(319 downto 288),
tdc_mesl4_i => wbg_mes(287 downto 256),
tdc_raw5_i => wbg_raw(191 downto 160),
tdc_mesh5_i => wbg_mes(383 downto 352),
tdc_mesl5_i => wbg_mes(351 downto 320),
tdc_raw6_i => wbg_raw(223 downto 192),
tdc_mesh6_i => wbg_mes(447 downto 416),
tdc_mesl6_i => wbg_mes(415 downto 384),
tdc_raw7_i => wbg_raw(255 downto 224),
tdc_mesh7_i => wbg_mes(511 downto 480),
tdc_mesl7_i => wbg_mes(479 downto 448),
irq_ie0_i => wbg_ie(0),
irq_ie1_i => wbg_ie(1),
irq_ie2_i => wbg_ie(2),
irq_ie3_i => wbg_ie(3),
irq_ie4_i => wbg_ie(4),
irq_ie5_i => wbg_ie(5),
irq_ie6_i => wbg_ie(6),
irq_ie7_i => wbg_ie(7)
-- end autogenerated connections
);
-- All synthesizers I know of will set unconnected bits to 0.
lut_a <= wbg_luta(g_RAW_COUNT-1 downto 0);
wbg_lutd(lut_d'range) <= lut_d;
his_a <= wbg_hisa(g_RAW_COUNT-1 downto 0);
wbg_hisd(his_d'range) <= his_d;
wbg_fcr(oc_freq'range) <= oc_freq;
wbg_fcsr(oc_sfreq'range) <= oc_sfreq;
g_connect: for i in 0 to g_CHANNEL_COUNT-1 generate
deskew((i+1)*(g_COARSE_COUNT+g_FP_COUNT)-1 downto i*(g_COARSE_COUNT+g_FP_COUNT))
<= wbg_des(i*64+g_COARSE_COUNT+g_FP_COUNT-1 downto i*64);
wbg_raw(i*32+g_RAW_COUNT-1 downto i*32)
<= raw((i+1)*g_RAW_COUNT-1 downto i*g_RAW_COUNT);
wbg_mes(i*64+g_COARSE_COUNT+g_FP_COUNT-1 downto i*64)
<= fp((i+1)*(g_COARSE_COUNT+g_FP_COUNT)-1 downto i*(g_COARSE_COUNT+g_FP_COUNT));
end generate;
wbg_pol(polarity'range) <= polarity;
wbg_ie(detect'range) <= detect;
end architecture;
rtl/Manifest.py 0 → 100644
View file @ 6896864b
files = [
"tdc_freqc.vhd",
"tdc_psync.vhd",
"tdc_delayline.vhd",
"tdc_lbc.vhd",
"tdc_ringosc.vhd",
"tdc_channel.vhd",
"tdc_divider.vhd",
"tdc_package.vhd",
"tdc_ordertaps.vhd",
"tdc_order_picker.vhd",
"tdc_channel_wb.vhd",
"tdc_wbgen2_pkg.vhd",
"tdc_core.vhd",
"xwb_urv_mcs.vhd"
];
modules = { "local" : [
"../ip_cores/general-cores",
"../ip_cores/urv-core"] };
rtl/build_wb.sh 0 → 100755
View file @ 6896864b
wbgen2 -H record_full -K ../testbench/include/tdc_channel_wb.vh -V tdc_channel_wb.vhd -p tdc_wbgen2_pkg.vhd tdc_channel_wb.wb
\ No newline at end of file
core/tdc.vhd → rtl/tdc.vhd
View file @ 6896864b
......@@ -127,7 +127,7 @@ signal oc_sfreq : std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
signal freeze_ack : std_logic;
begin
cmp_channelbank: tdc_channelbank
cmp_channelbank: entity work.tdc_channelbank
generic map(
g_CHANNEL_COUNT => g_CHANNEL_COUNT,
g_CARRY4_COUNT => g_CARRY4_COUNT,
......@@ -178,7 +178,7 @@ begin
oc_sfreq_o => oc_sfreq
);
cmp_controller: tdc_controller
cmp_controller: entity work.tdc_controller
generic map(
g_RAW_COUNT => g_RAW_COUNT,
g_FP_COUNT => g_FP_COUNT,
......
rtl/tdc_channel.vhd 0 → 100644
View file @ 6896864b
-------------------------------------------------------------------------------
-- TDC Core / CERN
-------------------------------------------------------------------------------
--
-- unit name: tdc_channel
--
-- author: Sebastien Bourdeauducq, sebastien@milkymist.org
--
-- description: Per-channel processing
--
-- references: http://www.ohwr.org/projects/tdc-core
--
-------------------------------------------------------------------------------
-- last changes:
-- 2011-11-07 SB Pre-inversion
-- 2011-10-25 SB Disable ring oscillator on reset
-- 2011-08-03 SB Created file
-------------------------------------------------------------------------------
-- Copyright (C) 2011 CERN
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, version 3 of the License.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- DESCRIPTION:
-- This contains the elements needed for each channel:
-- * Delay line
-- * Encoder
-- * LUT
-- * Deskew stage
-- * Online calibration ring oscillator
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tdc_package.all;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.tdc_wbgen2_pkg.all;
use work.gencores_pkg.all;
entity tdc_channel is
generic(
-- Number of CARRY4 elements.
g_CARRY4_COUNT : positive := 124;
-- Number of raw output bits.
g_RAW_COUNT : positive := 9;
-- Number of fractional part bits.
g_FP_COUNT : positive := 13;
-- Number of coarse counter bits.
g_COARSE_COUNT : positive := 25;
-- Length of the ring oscillator.
g_RO_LENGTH : positive := 31
);
port(
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
clk_tdc_i : in std_logic;
rst_tdc_n_i : in std_logic;
clk_cal_i : in std_logic;
-- Coarse counter and deskew inputs.
coarse_i : in std_logic_vector(g_COARSE_COUNT-1 downto 0);
-- Signal input.
signal_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
-- calib_sel_i : in std_logic;
-- Detection outputs.
--detect_o : out std_logic;
--polarity_o : out std_logic;
--raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
--fp_o : out std_logic_vector((g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
--raw_taps_o : out std_logic_vector(g_CARRY4_COUNT*4- 1 downto 0);
-- LUT access.
--lut_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
--lut_we_i : in std_logic;
--lut_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0);
--lut_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0);
-- Calibration ring oscillator.
-- ro_en_i : in std_logic;
-- ro_clk_o : out std_logic
);
end entity;
architecture rtl of tdc_channel is
signal calib_sel_d : std_logic;
signal muxed_signal : std_logic;
signal tdc_inv_input_signal : std_logic;
attribute keep : string;
attribute keep of tdc_inv_input_signal : signal is "true";
signal taps : std_logic_vector(4*g_CARRY4_COUNT-1 downto 0);
signal taps_latched : std_logic_vector(4*g_CARRY4_COUNT-1 downto 0);
signal ipolarity : std_logic;
signal polarity : std_logic;
signal polarity_d1 : std_logic;
signal polarity_d2 : std_logic;
signal detect_d1 : std_logic;
signal raw, raw_d1 : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal raw_d2 : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal lut_rvalue : std_logic_vector(g_FP_COUNT-1 downto 0);
signal ro_en : std_logic;
signal tdc_slave_out : t_wishbone_slave_out;
signal tdc_slave_in : t_wishbone_slave_in;
signal regs_in : t_tdc_in_registers;
signal regs_out : t_tdc_out_registers;
signal calib_next_sample : unsigned(14 downto 0);
signal calib_cur_sample : unsigned(14 downto 0);
signal calib_step_d : unsigned(14 downto 0);
signal calib_offset_d : unsigned(14 downto 0);
signal calib_p : std_logic;
signal calib_rst_n : std_logic;
signal rst_tdc : std_logic;
signal ro_clk : std_logic;
signal detect : std_logic;
signal prev_taps_zero : std_logic;
signal taps_latched_ready : std_logic;
constant c_max_tap_bank : integer := (g_CARRY4_COUNT*4 + 31) / 32;
function f_max(x : integer; y : integer) return integer is
begin
if (x > y) then
return x;
else
return y;
end if;
end f_max;
function f_clamp(x : integer; max : integer) return integer is
begin
if (x > max) then
return max;
else
return x;
end if;
end f_clamp;
begin
rst_tdc <= not rst_tdc_n_i;
--slave_o <= tdc_slave_out;
-- tdc_slave_in <= slave_i;
U_Clock_Crossing : xwb_clock_crossing
port map (
slave_clk_i => clk_sys_i,
slave_rst_n_i => rst_sys_n_i,
slave_i => slave_i,
slave_o => slave_o,
master_clk_i => clk_tdc_i,
master_rst_n_i => rst_tdc_n_i,
master_i => tdc_slave_out,
master_o => tdc_slave_in);
U_WB_Slave : entity work.tdc_channel_wb
port map (
rst_n_i => rst_tdc_n_i,
clk_sys_i => clk_tdc_i,
slave_i => tdc_slave_in,
slave_o => tdc_slave_out,
int_o => open,
regs_i => regs_in,
regs_o => regs_out);
U_Sync_Calib_Sel : gc_sync_ffs
port map (
clk_i => clk_cal_i,
rst_n_i => rst_tdc_n_i,
data_i => regs_out.calr_cal_mode_o,
synced_o => calib_sel_d);
U_Sync_Calib_Reset : gc_sync_ffs
port map (
clk_i => clk_cal_i,
rst_n_i => '1',
data_i => rst_tdc_n_i,
synced_o => calib_rst_n);
-- register calibration select signal to avoid glitches
p_reg_calib_regs : process(clk_cal_i)
begin
if rising_edge(clk_cal_i) then
if calib_rst_n = '0' then
calib_step_d <= (others => '0');
calib_offset_d <= (others => '0');
else
calib_step_d <= unsigned(regs_out.calr_cal_step_o);
calib_offset_d <= unsigned(regs_out.calr_cal_offset_o);
end if;
end if;
end process;
p_calib_pattern_gen : process(clk_cal_i)
begin
if rising_edge(clk_cal_i) then
if calib_rst_n = '0' then
calib_cur_sample <= (others => '0');
calib_next_sample <= (others => '0');
calib_p <= '0';
elsif calib_cur_sample = resize(calib_next_sample + calib_offset_d, calib_cur_sample'Length) and calib_step_d /= 0 then
calib_next_sample <= calib_next_sample + calib_step_d;
calib_cur_sample <= calib_cur_sample + 1;
calib_p <= '1';
elsif calib_step_d /= 0 then
calib_cur_sample <= calib_cur_sample + 1;
calib_p <= '0';
end if;
end if;
end process;
muxed_signal <= calib_p when calib_sel_d = '1' else signal_i;
tdc_inv_input_signal <= muxed_signal xor not ipolarity;
cmp_delayline : entity work.tdc_delayline
generic map(
g_WIDTH => g_CARRY4_COUNT
)
port map(
clk_i => clk_tdc_i,
reset_i => rst_tdc,
signal_i => tdc_inv_input_signal,
taps_o => taps
);
cmp_lbc : entity work.tdc_lbc
generic map(
g_N => g_RAW_COUNT,
g_NIN => g_CARRY4_COUNT*4,
g_IGNORE => 2
)
port map(
clk_i => clk_tdc_i,
reset_i => rst_tdc,
d_i => taps,
ipolarity_o => ipolarity,
polarity_o => polarity,
count_o => raw
);
process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc = '1' then
prev_taps_zero <= '1';
taps_latched_ready <= '0';
else
if regs_out.raw_csr_ack_o = '1' then
taps_latched_ready <= '0';
end if;
if unsigned(taps) = 0 then
prev_taps_zero <= '1';
elsif prev_taps_zero = '1' and unsigned(taps) /= 0 and taps_latched_ready = '0' then
taps_latched <= taps;
taps_latched_ready <= '1';
prev_taps_zero <= '0';
end if;
end if;
end if;
end process;
regs_in.raw_csr_valid_i <= taps_latched_ready;
process(clk_tdc_i)
variable idx : integer;
variable idx_h, idx_l : integer;
begin
if rising_edge(clk_sys_i) then
idx := to_integer(unsigned(regs_out.raw_bank_o));
idx_l := idx * 32;
idx_h := f_clamp(idx_l + 31, g_CARRY4_COUNT*4-1);
regs_in.raw_taps_i <= std_logic_vector(resize(unsigned(taps_latched( idx_h downto idx_l)), 32));
end if;
end process;
--cmp_lut : generic_dpram
-- generic map(
-- g_data_width => g_FP_COUNT,
-- g_size => 2**g_RAW_COUNT,
-- g_with_byte_enable => false,
-- g_addr_conflict_resolution => "read_first",
-- g_init_file => "",
-- g_dual_clock => false
-- )
-- port map(
-- clka_i => clk_i,
-- clkb_i => '0',
-- wea_i => '0',
-- bwea_i => (others => '0'),
-- aa_i => raw,
-- da_i => (others => '0'),
-- qa_o => lut_rvalue,
-- web_i => lut_we_i,
-- bweb_i => (others => '0'),
-- ab_i => lut_a_i,
-- db_i => lut_d_i,
-- qb_o => lut_d_o
-- );
cmp_ringosc : entity work.tdc_ringosc
generic map(
g_LENGTH => g_RO_LENGTH
)
port map(
en_i => ro_en,
clk_o => ro_clk
);
ro_en <= regs_out.csr_ro_en_o and rst_tdc_n_i;
detect_d1 <= polarity_d1 xor polarity_d2;
process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc = '1' then
detect <= '0';
polarity_d1 <= '1';
polarity_d2 <= '1';
raw_d1 <= (others => '0');
raw_d2 <= (others => '0');
else
detect <= detect_d1;
polarity_d1 <= polarity;
raw_d1 <= raw;
if detect_d1 = '1' then
polarity_d2 <= polarity_d1;
raw_d2 <= raw_d1;
end if;
end if;
end if;
end process;
-- polarity_o <= polarity_d2;
-- raw_o <= raw_d2;
-- Combine coarse counter value and deskew.
--process(clk_i)
--begin
-- if rising_edge(clk_i) then
-- if reset_i = '1' then
-- fp_o <= (others => '0');
-- else
-- if detect_d1 = '1' then
-- fp_o <= std_logic_vector(
-- (resize(unsigned(coarse_i), g_FP_COUNT+g_COARSE_COUNT) sll g_FP_COUNT)
-- - unsigned(lut_rvalue)
-- + unsigned(deskew_i)
-- );
-- end if;
-- end if;
-- end if;
--end process;
regs_in.csr_valid_i <= '0';
regs_in.csr_rdy_i <= '0';
end architecture;
rtl/tdc_channel_wb.vhd 0 → 100644
View file @ 6896864b
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC
---------------------------------------------------------------------------------------
-- File : tdc_channel_wb.vhd
-- Author : auto-generated by wbgen2 from tdc_channel_wb.wb
-- Created : Tue Sep 11 22:15:48 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc_channel_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.tdc_wbgen2_pkg.all;
entity tdc_channel_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_tdc_in_registers;
regs_o : out t_tdc_out_registers
);
end tdc_channel_wb;
architecture syn of tdc_channel_wb is
signal tdc_csr_rst_dly0 : std_logic ;
signal tdc_csr_rst_int : std_logic ;
signal tdc_csr_ro_en_int : std_logic ;
signal tdc_calr_cal_mode_int : std_logic ;
signal tdc_calr_cal_step_int : std_logic_vector(14 downto 0);
signal tdc_calr_cal_offset_int : std_logic_vector(14 downto 0);
signal tdc_raw_csr_ack_dly0 : std_logic ;
signal tdc_raw_csr_ack_int : std_logic ;
signal tdc_raw_bank_int : std_logic_vector(7 downto 0);
signal tdc_luta_int : std_logic_vector(15 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
tdc_csr_rst_int <= '0';
tdc_csr_ro_en_int <= '0';
tdc_calr_cal_mode_int <= '0';
tdc_calr_cal_step_int <= "000000000000000";
tdc_calr_cal_offset_int <= "000000000000000";
tdc_raw_csr_ack_int <= '0';
tdc_raw_bank_int <= "00000000";
tdc_luta_int <= "0000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
tdc_csr_rst_int <= '0';
tdc_raw_csr_ack_int <= '0';
ack_in_progress <= '0';
else
end if;
else
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (slave_i.we = '1') then
tdc_csr_rst_int <= wrdata_reg(0);
tdc_csr_ro_en_int <= wrdata_reg(3);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= regs_i.csr_rdy_i;
rddata_reg(2) <= regs_i.csr_valid_i;
rddata_reg(3) <= tdc_csr_ro_en_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (slave_i.we = '1') then
tdc_calr_cal_mode_int <= wrdata_reg(0);
tdc_calr_cal_step_int <= wrdata_reg(15 downto 1);
tdc_calr_cal_offset_int <= wrdata_reg(30 downto 16);
end if;
rddata_reg(0) <= tdc_calr_cal_mode_int;
rddata_reg(15 downto 1) <= tdc_calr_cal_step_int;
rddata_reg(30 downto 16) <= tdc_calr_cal_offset_int;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (slave_i.we = '1') then
tdc_raw_csr_ack_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= regs_i.raw_csr_valid_i;
rddata_reg(1) <= '0';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (slave_i.we = '1') then
tdc_raw_bank_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= tdc_raw_bank_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.raw_taps_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (slave_i.we = '1') then
tdc_luta_int <= wrdata_reg(15 downto 0);
end if;
rddata_reg(15 downto 0) <= tdc_luta_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.lutd_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.fcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.fcsr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
slave_o.dat <= rddata_reg;
-- Reset
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tdc_csr_rst_dly0 <= '0';
regs_o.csr_rst_o <= '0';
elsif rising_edge(clk_sys_i) then
tdc_csr_rst_dly0 <= tdc_csr_rst_int;
regs_o.csr_rst_o <= tdc_csr_rst_int and (not tdc_csr_rst_dly0);
end if;
end process;
-- Ready
-- TS valid
-- Enable ring oscillator
regs_o.csr_ro_en_o <= tdc_csr_ro_en_int;
-- Calibration mode select
regs_o.calr_cal_mode_o <= tdc_calr_cal_mode_int;
-- Calibration step select
regs_o.calr_cal_step_o <= tdc_calr_cal_step_int;
-- Calibration offset select
regs_o.calr_cal_offset_o <= tdc_calr_cal_offset_int;
-- TS valid
-- TS ack
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tdc_raw_csr_ack_dly0 <= '0';
regs_o.raw_csr_ack_o <= '0';
elsif rising_edge(clk_sys_i) then
tdc_raw_csr_ack_dly0 <= tdc_raw_csr_ack_int;
regs_o.raw_csr_ack_o <= tdc_raw_csr_ack_int and (not tdc_raw_csr_ack_dly0);
end if;
end process;
-- raw bank select
regs_o.raw_bank_o <= tdc_raw_bank_int;
-- raw taps
-- Address
regs_o.luta_o <= tdc_luta_int;
-- Data
-- Result
-- Result
rwaddr_reg <= slave_i.adr(5 downto 2);
slave_o.stall <= (not ack_sreg(0)) and (slave_i.stb and slave_i.cyc);
slave_o.err <= '0';
slave_o.rty <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
slave_o.ack <= ack_sreg(0);
end syn;
rtl/tdc_channel_wb.wb 0 → 100644
View file @ 6896864b
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral
{
name = "TDC";
description = "Time to digital converter (signle channel).";
hdl_entity = "tdc_channel_wb";
prefix = "tdc";
reg {
name = "Control and status";
description = "Control and status.";
prefix = "csr";
field {
name = "Reset";
prefix = "rst";
type = MONOSTABLE;
};
field {
name = "Ready";
prefix = "rdy";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TS valid";
prefix = "valid";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Enable ring oscillator";
prefix = "ro_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Calibration control";
prefix = "calr";
field {
name = "Calibration mode select";
prefix = "cal_mode";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Calibration step select";
prefix = "cal_step";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Calibration offset select";
prefix = "cal_offset";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TS raw CSR";
prefix = "raw_csr";
field {
name = "TS valid";
prefix = "valid";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TS ack";
prefix = "ack";
type = MONOSTABLE;
};
};
reg {
name = "TS raw taps bank select";
prefix = "raw_bank";
field {
name = "raw bank select";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TS raw taps";
prefix = "raw_taps";
field {
name = "raw taps";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "LUT read address";
description = "LUT address to read when debugging.";
prefix = "luta";
field {
name = "Address";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "LUT read data";
description = "LUT data readback for debugging.";
prefix = "lutd";
field {
name = "Data";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Frequency counter current value";
description = "Reports the latest measurement result of the frequency counter for debugging.";
prefix = "fcr";
field {
name = "Result";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Frequency counter stored value";
description = "Reports the latest stored measurement result of the frequency counter for debugging.";
prefix = "fcsr";
field {
name = "Result";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
core/tdc_channelbank.vhd → rtl/tdc_channelbank.vhd
View file @ 6896864b
......@@ -109,7 +109,7 @@ end entity;
architecture rtl of tdc_channelbank is
begin
g_single: if g_CHANNEL_COUNT = 1 generate
cmp_channelbank: tdc_channelbank_single
cmp_channelbank: entity work.tdc_channelbank_single
generic map(
g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT,
......@@ -160,7 +160,7 @@ begin
);
end generate;
g_multi: if g_CHANNEL_COUNT > 1 generate
cmp_channelbank: tdc_channelbank_multi
cmp_channelbank: entity work.tdc_channelbank_multi
generic map(
g_CHANNEL_COUNT => g_CHANNEL_COUNT,
g_CARRY4_COUNT => g_CARRY4_COUNT,
......
core/tdc_channelbank_multi.vhd → rtl/tdc_channelbank_multi.vhd
View file @ 6896864b
......@@ -133,7 +133,7 @@ begin
begin
this_calib_sel <= current_channel_onehot(i) and calib_sel_i;
this_lut_we <= current_channel_onehot(i) and lut_we_i;
cmp_channel: tdc_channel
cmp_channel: entity work.tdc_channel
generic map(
g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT,
......@@ -192,7 +192,7 @@ begin
his_full_a <= current_channel & his_a_i;
-- Frequency counter.
cmp_freqc: tdc_freqc
cmp_freqc: entity work.tdc_freqc
generic map(
g_COUNTER_WIDTH => g_FCOUNTER_WIDTH,
g_TIMER_WIDTH => g_FTIMER_WIDTH
......
core/tdc_channelbank_single.vhd → rtl/tdc_channelbank_single.vhd
View file @ 6896864b
......@@ -105,7 +105,7 @@ signal freq : std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
signal sfreq_s : std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
begin
-- Per-channel processing.
cmp_channel: tdc_channel
cmp_channel: entity work.tdc_channel
generic map(
g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT,
......@@ -162,7 +162,7 @@ begin
);
-- Frequency counter.
cmp_freqc: tdc_freqc
cmp_freqc: entity work.tdc_freqc
generic map(
g_COUNTER_WIDTH => g_FCOUNTER_WIDTH,
g_TIMER_WIDTH => g_FTIMER_WIDTH
......
core/tdc_controller.vhd → rtl/tdc_controller.vhd
View file @ 6896864b
......@@ -185,7 +185,7 @@ begin
end process;
-- divider
cmp_divider: tdc_divider
cmp_divider: entity work.tdc_divider
generic map(
g_WIDTH => g_FP_COUNT+g_FCOUNTER_WIDTH
)
......
rtl/tdc_core.vhd 0 → 100644
View file @ 6896864b
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity tdc_core is
generic (
g_CARRY4_COUNT : positive := 124;
g_RAW_COUNT : positive := 9;
g_FP_COUNT : positive := 13;
g_COARSE_COUNT : positive := 25;
g_RO_LENGTH : positive := 31);
port (
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
clk_tdc_i : in std_logic;
rst_tdc_n_i : in std_logic;
clk_cal_i : in std_logic;
coarse_i : in std_logic_vector(g_COARSE_COUNT-1 downto 0) := (others => '0');
signal_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
dbg_txd_o : out std_logic;
dbg_rxd_i : in std_logic := '1');
end entity tdc_core;
architecture rtl of tdc_core is
constant c_cnx_slave_ports : integer := 2;
constant c_cnx_master_ports : integer := 3;
constant c_master_host : integer := 0;
constant c_master_urv : integer := 1;
constant c_slave_csr : integer := 0;
constant c_slave_vuart : integer := 1;
constant c_slave_tdc : integer := 2;
signal cnx_master_in : t_wishbone_master_in_array(c_cnx_master_ports-1 downto 0);
signal cnx_master_out : t_wishbone_master_out_array(c_cnx_master_ports-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_cnx_slave_ports-1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_cnx_slave_ports-1 downto 0);
constant c_cfg_base_addr : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
(c_slave_csr => x"00000000",
c_slave_vuart => x"00001000",
c_slave_tdc => x"00002000"
);
constant c_cfg_base_mask : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
(c_slave_csr => x"0000f000",
c_slave_vuart => x"0000f000",
c_slave_tdc => x"0000f000"
);
begin
slave_o <= cnx_slave_out(c_master_host);
cnx_slave_in(c_master_host) <= slave_i;
U_MCU : entity work.xwb_urv_mcs
generic map (
g_iram_size => 65536,
g_with_host_if => true
)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
host_wb_i => cnx_master_out(c_slave_csr),
host_wb_o => cnx_master_in(c_slave_csr),
dwb_o => cnx_slave_in(c_master_urv),
dwb_i => cnx_slave_out(c_master_urv));
U_Host_Intercon : xwb_crossbar
generic map (
g_num_masters => c_cnx_slave_ports,
g_num_slaves => c_cnx_master_ports,
g_registered => true,
g_address => c_cfg_base_addr,
g_mask => c_cfg_base_mask)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
U_CH1 : entity work.tdc_channel
generic map (
g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT,
g_FP_COUNT => g_FP_COUNT,
g_COARSE_COUNT => g_COARSE_COUNT,
g_RO_LENGTH => g_RO_LENGTH)
port map (
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
clk_tdc_i => clk_tdc_i,
rst_tdc_n_i => rst_tdc_n_i,
clk_cal_i => clk_cal_i,
coarse_i => coarse_i,
signal_i => signal_i,
slave_i => cnx_master_out(c_slave_tdc),
slave_o => cnx_master_in(c_slave_tdc));
U_VUART : xwb_simple_uart
generic map (
g_with_virtual_uart => true,
g_with_physical_uart => true,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_slave_vuart),
slave_o => cnx_master_in(c_slave_vuart),
uart_rxd_i => dbg_rxd_i,
uart_txd_o => dbg_txd_o);
end rtl;
core/tdc_delayline.vhd → rtl/tdc_delayline.vhd
View file @ 6896864b
......@@ -41,8 +41,8 @@
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
--library unisim;
--use unisim.vcomponents.all;
library work;
use work.tdc_package.all;
......@@ -96,6 +96,7 @@ begin
S => "1111"
);
end generate;
end generate;
-- double latch the output
......@@ -123,11 +124,13 @@ begin
end generate;
-- sort taps by increasing delays, according to static timing model
cmp_ordertaps: tdc_ordertaps
cmp_ordertaps: entity work.tdc_ordertaps
generic map(
g_WIDTH => g_WIDTH
)
port map(
clk_i => clk_i,
rst_i => reset_i,
unsorted_i => taps_rev,
sorted_o => taps_rev_sorted
);
......
core/tdc_freqc.vhd → rtl/tdc_freqc.vhd
View file @ 6896864b
......@@ -92,14 +92,14 @@ begin
end process;
-- Synchronisers.
cmp_sync_start: tdc_psync
cmp_sync_start: entity work.tdc_psync
port map(
clk_src_i => clk_i,
p_i => start,
clk_dst_i => clk_m_i,
p_o => m_start
);
cmp_sync_stop: tdc_psync
cmp_sync_stop: entity work.tdc_psync
port map(
clk_src_i => clk_i,
p_i => stop,
......@@ -107,7 +107,7 @@ begin
p_o => m_stop
);
cmp_sync_stop_ack: tdc_psync
cmp_sync_stop_ack: entity work.tdc_psync
port map(
clk_src_i => clk_m_i,
p_i => m_stop,
......
rtl/tdc_hostif.vhd 0 → 100644
View file @ 6896864b
-------------------------------------------------------------------------------
-- TDC Core / CERN
-------------------------------------------------------------------------------
--
-- unit name: tdc_hostif
--
-- author: Sebastien Bourdeauducq, sebastien@milkymist.org
--
-- description: Host interface for the TDC core
--
-- references: http://www.ohwr.org/projects/tdc-core
--
-------------------------------------------------------------------------------
-- last changes:
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-08-27 SB Reduced supported channel count to 8
-- 2011-08-26 SB Created file
-------------------------------------------------------------------------------
-- Copyright (C) 2011 CERN
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, version 3 of the License.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- DESCRIPTION:
-- Top level module of the TDC core, contains all logic including the optional
-- host interface. It instantiates the basic TDC core and a Wishbone interface.
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tdc_package.all;
use work.tdc_hostif_package.all;
use work.wishbone_pkg.all;
entity tdc_hostif is
generic(
g_CHANNEL_COUNT : positive := 1;
g_CARRY4_COUNT : positive := 124;
g_RAW_COUNT : positive := 9;
g_FP_COUNT : positive := 13;
g_EXHIS_COUNT : positive := 4;
g_COARSE_COUNT : positive := 25;
g_RO_LENGTH : positive := 31;
g_FCOUNTER_WIDTH : positive := 13;
g_FTIMER_WIDTH : positive := 14
);
port(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
timestamp_o : t_tdc_timestamp_array(g_CHANNEL_COUNT-1 downto 0);
timestamp_valid_o : out std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
timestamp_ready_i : in std_logic_vector(g_CHANNEL_COUNT-1 downto 0) := (others => '1');
cc_rst_i : in std_logic := '0';
cc_cy_o : out std_logic;
signal_i : in std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
calib_i : in std_logic_vector(g_CHANNEL_COUNT-1 downto 0) := (others => '0')
);
end entity;
architecture rtl of tdc_hostif is
signal reset, reset_sw : std_logic;
signal ready : std_logic;
signal cc_cy : std_logic;
signal deskew : std_logic_vector(g_CHANNEL_COUNT*(g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
signal detect : std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
signal polarity : std_logic_vector(g_CHANNEL_COUNT-1 downto 0);
signal raw : std_logic_vector(g_CHANNEL_COUNT*g_RAW_COUNT-1 downto 0);
signal fp : std_logic_vector(g_CHANNEL_COUNT*(g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
signal freeze_req : std_logic;
signal freeze_ack : std_logic;
signal cs_next : std_logic;
signal cs_last : std_logic;
signal calib_sel : std_logic;
signal lut_a : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal lut_d : std_logic_vector(g_FP_COUNT-1 downto 0);
signal his_a : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal his_d : std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
signal oc_start : std_logic;
signal oc_ready : std_logic;
signal oc_freq : std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
signal oc_sfreq : std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
signal wbg_luta : std_logic_vector(15 downto 0);
signal wbg_lutd : std_logic_vector(31 downto 0);
signal wbg_hisa : std_logic_vector(15 downto 0);
signal wbg_hisd : std_logic_vector(31 downto 0);
signal wbg_fcr : std_logic_vector(31 downto 0);
signal wbg_fcsr : std_logic_vector(31 downto 0);
-- maximum number of channels the host interface can support
constant c_NCHAN : positive := 8;
signal wbg_des : std_logic_vector(c_NCHAN*64-1 downto 0);
signal wbg_pol : std_logic_vector(c_NCHAN-1 downto 0);
signal wbg_raw : std_logic_vector(c_NCHAN*32-1 downto 0);
signal wbg_mes : std_logic_vector(c_NCHAN*64-1 downto 0);
signal wbg_ie : std_logic_vector(c_NCHAN-1 downto 0);
begin
p_software_reset:process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
reset <= '1';
else
reset <= reset_sw;
end if;
end if;
end process;
cmp_tdc : entity work.tdc
generic map(
g_CHANNEL_COUNT => g_CHANNEL_COUNT,
g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT,
g_FP_COUNT => g_FP_COUNT,
g_EXHIS_COUNT => g_EXHIS_COUNT,
g_COARSE_COUNT => g_COARSE_COUNT,
g_RO_LENGTH => g_RO_LENGTH,
g_FCOUNTER_WIDTH => g_FCOUNTER_WIDTH,
g_FTIMER_WIDTH => g_FTIMER_WIDTH
)
port map(
clk_i => clk_sys_i,
reset_i => reset,
ready_o => ready,
cc_rst_i => cc_rst_i,
cc_cy_o => cc_cy,
deskew_i => deskew,
signal_i => signal_i,
calib_i => calib_i,
detect_o => detect,
polarity_o => polarity,
raw_o => raw,
fp_o => fp,
freeze_req_i => freeze_req,
freeze_ack_o => freeze_ack,
cs_next_i => cs_next,
cs_last_o => cs_last,
calib_sel_i => calib_sel,
lut_a_i => lut_a,
lut_d_o => lut_d,
his_a_i => his_a,
his_d_o => his_d,
oc_start_i => oc_start,
oc_ready_o => oc_ready,
oc_freq_o => oc_freq,
oc_sfreq_o => oc_sfreq
);
cc_cy_o <= cc_cy;
cmp_wb : entity work.tdc_wb
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => slave_i.adr(7 downto 2),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
wb_int_o => int_o,
tdc_cs_rst_o => reset_sw,
tdc_cs_rdy_i => ready,
irq_isc_i => ready,
irq_icc_i => cc_cy,
tdc_dctl_req_o => freeze_req,
tdc_dctl_ack_i => freeze_ack,
tdc_csel_next_o => cs_next,
tdc_csel_last_i => cs_last,
tdc_cal_o => calib_sel,
tdc_fcc_st_o => oc_start,
tdc_fcc_rdy_i => oc_ready,
tdc_luta_o => wbg_luta,
tdc_lutd_i => wbg_lutd,
tdc_hisa_o => wbg_hisa,
tdc_hisd_i => wbg_hisd,
tdc_fcr_i => wbg_fcr,
tdc_fcsr_i => wbg_fcsr,
tdc_pol_i => wbg_pol,
-- begin autogenerated connections
tdc_desh0_o => wbg_des(63 downto 32),
tdc_desl0_o => wbg_des(31 downto 0),
tdc_desh1_o => wbg_des(127 downto 96),
tdc_desl1_o => wbg_des(95 downto 64),
tdc_desh2_o => wbg_des(191 downto 160),
tdc_desl2_o => wbg_des(159 downto 128),
tdc_desh3_o => wbg_des(255 downto 224),
tdc_desl3_o => wbg_des(223 downto 192),
tdc_desh4_o => wbg_des(319 downto 288),
tdc_desl4_o => wbg_des(287 downto 256),
tdc_desh5_o => wbg_des(383 downto 352),
tdc_desl5_o => wbg_des(351 downto 320),
tdc_desh6_o => wbg_des(447 downto 416),
tdc_desl6_o => wbg_des(415 downto 384),
tdc_desh7_o => wbg_des(511 downto 480),
tdc_desl7_o => wbg_des(479 downto 448),
tdc_raw0_i => wbg_raw(31 downto 0),
tdc_mesh0_i => wbg_mes(63 downto 32),
tdc_mesl0_i => wbg_mes(31 downto 0),
tdc_raw1_i => wbg_raw(63 downto 32),
tdc_mesh1_i => wbg_mes(127 downto 96),
tdc_mesl1_i => wbg_mes(95 downto 64),
tdc_raw2_i => wbg_raw(95 downto 64),
tdc_mesh2_i => wbg_mes(191 downto 160),
tdc_mesl2_i => wbg_mes(159 downto 128),
tdc_raw3_i => wbg_raw(127 downto 96),
tdc_mesh3_i => wbg_mes(255 downto 224),
tdc_mesl3_i => wbg_mes(223 downto 192),
tdc_raw4_i => wbg_raw(159 downto 128),
tdc_mesh4_i => wbg_mes(319 downto 288),
tdc_mesl4_i => wbg_mes(287 downto 256),
tdc_raw5_i => wbg_raw(191 downto 160),
tdc_mesh5_i => wbg_mes(383 downto 352),
tdc_mesl5_i => wbg_mes(351 downto 320),
tdc_raw6_i => wbg_raw(223 downto 192),
tdc_mesh6_i => wbg_mes(447 downto 416),
tdc_mesl6_i => wbg_mes(415 downto 384),
tdc_raw7_i => wbg_raw(255 downto 224),
tdc_mesh7_i => wbg_mes(511 downto 480),
tdc_mesl7_i => wbg_mes(479 downto 448),
irq_ie0_i => wbg_ie(0),
irq_ie1_i => wbg_ie(1),
irq_ie2_i => wbg_ie(2),
irq_ie3_i => wbg_ie(3),
irq_ie4_i => wbg_ie(4),
irq_ie5_i => wbg_ie(5),
irq_ie6_i => wbg_ie(6),
irq_ie7_i => wbg_ie(7)
-- end autogenerated connections
);
slave_o.rty <= '0';
slave_o.err <= '0';
-- All synthesizers I know of will set unconnected bits to 0.
lut_a <= wbg_luta(g_RAW_COUNT-1 downto 0);
wbg_lutd(lut_d'range) <= lut_d;
his_a <= wbg_hisa(g_RAW_COUNT-1 downto 0);
wbg_hisd(his_d'range) <= his_d;
wbg_fcr(oc_freq'range) <= oc_freq;
wbg_fcsr(oc_sfreq'range) <= oc_sfreq;
g_connect : for i in 0 to g_CHANNEL_COUNT-1 generate
deskew((i+1)*(g_COARSE_COUNT+g_FP_COUNT)-1 downto i*(g_COARSE_COUNT+g_FP_COUNT))
<= wbg_des(i*64+g_COARSE_COUNT+g_FP_COUNT-1 downto i*64);
wbg_raw(i*32+g_RAW_COUNT-1 downto i*32)
<= raw((i+1)*g_RAW_COUNT-1 downto i*g_RAW_COUNT);
wbg_mes(i*64+g_COARSE_COUNT+g_FP_COUNT-1 downto i*64)
<= fp((i+1)*(g_COARSE_COUNT+g_FP_COUNT)-1 downto i*(g_COARSE_COUNT+g_FP_COUNT));
end generate;
wbg_pol(polarity'range) <= polarity;
wbg_ie(detect'range) <= detect;
end architecture;
rtl/tdc_order_picker.vhd 0 → 100644
View file @ 6896864b
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tdc_order_picker is
generic(
g_RANGE : integer := 5
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
cfg_i : in std_logic_vector(2*g_RANGE downto 0);
we_i : in std_logic;
unsorted_i : in std_logic_vector(2*g_RANGE downto 0);
picked_o : out std_logic
);
end entity;
architecture rtl of tdc_order_picker is
signal mask : std_logic_vector(2*g_RANGE downto 0);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '0' then
mask <= (others => '0');
mask(g_RANGE) <= '1';
elsif we_i = '1' then
mask <= cfg_i;
end if;
end if;
end process;
picked_o <= '0' when unsigned(mask and unsorted_i) = 0 else '1';
end rtl;
rtl/tdc_ordertaps.vhd 0 → 100644
View file @ 6896864b
-- This file was autogenerated by ordertaps.py
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tdc_package.all;
entity tdc_ordertaps is
generic(
g_WIDTH: positive;
g_LUT_ADDR_BITS : positive := 10;
g_RANGE : integer := 2
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
lut_addr_i : in std_logic_vector(g_LUT_ADDR_BITS-1 downto 0) := (others => '0');
lut_data_i : in std_logic_vector(2*g_RANGE downto 0) := (others => '0');
lut_we_i : in std_logic := '0';
unsorted_i : in std_logic_vector(4*g_WIDTH-1 downto 0);
sorted_o : out std_logic_vector(4*g_WIDTH-1 downto 0)
);
end entity;
architecture rtl of tdc_ordertaps is
signal we : std_logic_vector(4*g_WIDTH-1 downto 0);
signal in_vec : std_logic_vector(4*g_WIDTH-1 + 2*g_RANGE+1 downto 0);
begin
process(unsorted_i)
begin
in_vec <= (others => '0');
in_vec( 4*g_WIDTH-1+g_RANGE-1 downto g_RANGE-1 ) <= unsorted_i;
end process;
gen_pickers: for i in 0 to g_WIDTH*4 -1 generate
process(lut_we_i, lut_addr_i) begin
if TO_INTEGER(unsigned(lut_addr_i)) = i then
we(i) <= '1';
else
we(i) <= '0';
end if;
end process;
cmp_picker: entity work.tdc_order_picker
generic map (
g_RANGE => g_RANGE)
port map (
clk_i => clk_i,
rst_i => rst_i,
cfg_i => lut_data_i,
we_i => we(i),
unsorted_i => in_vec(i + 2*g_RANGE downto i),
picked_o => sorted_o(i));
end generate gen_pickers;
end architecture;
rtl/tdc_package.vhd 0 → 100644
View file @ 6896864b
-------------------------------------------------------------------------------
-- TDC Core / CERN
-------------------------------------------------------------------------------
--
-- unit name: tdc_package
--
-- author: Sebastien Bourdeauducq, sebastien@milkymist.org
--
-- description: Component declarations for the TDC core
--
-- references: http://www.ohwr.org/projects/tdc-core
--
-------------------------------------------------------------------------------
-- last changes:
-- 2011-11-07 SB Pre-inversion
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-10-25 SB Added single/multi channel bank components
-- 2011-08-03 SB Created file
-------------------------------------------------------------------------------
-- Copyright (C) 2011 CERN
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, version 3 of the License.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- DESCRIPTION:
-- This contains component declarations for all the modules of the TDC core.
-- It is used both internally to instantiate modules, and by the user to
-- instantiate the top-level "tdc" module.
library ieee;
use ieee.std_logic_1164.all;
package tdc_package is
type t_tdc_timestamp is record
slope : std_logic;
channel : std_logic_vector(2 downto 0);
frac : std_logic_vector(11 downto 0);
coarse : std_logic_vector(31 downto 0);
tai : std_logic_vector(31 downto 0);
seq : std_logic_vector(31 downto 0);
end record;
type t_tdc_timestamp_array is array(integer range<>) of t_tdc_timestamp;
component CARRY4 is
port (
CO : out std_logic_vector(3 downto 0);
O : out std_logic_vector(3 downto 0);
CI : in std_ulogic := 'L';
CYINIT : in std_ulogic := 'L';
DI : in std_logic_vector(3 downto 0);
S : in std_logic_vector(3 downto 0));
end component CARRY4;
component FDR is
generic (
INIT : bit);
port (
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic);
end component FDR;
component LUT2 is
generic (
INIT : bit_vector);
port (
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic);
end component LUT2;
component LUT1 is
generic (
INIT : bit_vector);
port (
O : out std_ulogic;
I0 : in std_ulogic);
end component LUT1;
end package;
core/tdc_ringosc.vhd → rtl/tdc_ringosc.vhd
View file @ 6896864b
......@@ -36,9 +36,6 @@
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.tdc_package.all;
......
hostif/tdc_wb.vhd → rtl/tdc_wb.vhd
View file @ 6896864b
......@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for TDC
---------------------------------------------------------------------------------------
-- File : tdc_wb.vhd
-- Author : auto-generated by wbgen2 from tdc.wb
-- Created : Tue Oct 25 16:54:19 2011
-- Author : auto-generated by wbgen2 from tdc_wb.wb
-- Created : Tue Sep 4 18:51:14 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -18,16 +18,19 @@ use work.wbgen2_pkg.all;
entity tdc_wb is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
-- Port for MONOSTABLE field: 'Reset' in reg: 'Control and status'
tdc_cs_rst_o : out std_logic;
-- Port for BIT field: 'Ready' in reg: 'Control and status'
......@@ -199,22 +202,15 @@ signal rwaddr_reg : std_logic_vector(5 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
......@@ -246,7 +242,7 @@ begin
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
elsif rising_edge(bus_clock_int) then
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
......@@ -267,10 +263,8 @@ begin
when "000000" =>
if (wb_we_i = '1') then
tdc_cs_rst_int <= wrdata_reg(0);
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
else
rddata_reg(0) <= 'X';
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= tdc_cs_rdy_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
......@@ -302,140 +296,123 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "000001" =>
if (wb_we_i = '1') then
tdc_desh0_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desh0_int;
end if;
rddata_reg(31 downto 0) <= tdc_desh0_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000010" =>
if (wb_we_i = '1') then
tdc_desl0_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desl0_int;
end if;
rddata_reg(31 downto 0) <= tdc_desl0_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000011" =>
if (wb_we_i = '1') then
tdc_desh1_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desh1_int;
end if;
rddata_reg(31 downto 0) <= tdc_desh1_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000100" =>
if (wb_we_i = '1') then
tdc_desl1_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desl1_int;
end if;
rddata_reg(31 downto 0) <= tdc_desl1_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000101" =>
if (wb_we_i = '1') then
tdc_desh2_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desh2_int;
end if;
rddata_reg(31 downto 0) <= tdc_desh2_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000110" =>
if (wb_we_i = '1') then
tdc_desl2_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desl2_int;
end if;
rddata_reg(31 downto 0) <= tdc_desl2_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000111" =>
if (wb_we_i = '1') then
tdc_desh3_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desh3_int;
end if;
rddata_reg(31 downto 0) <= tdc_desh3_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001000" =>
if (wb_we_i = '1') then
tdc_desl3_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desl3_int;
end if;
rddata_reg(31 downto 0) <= tdc_desl3_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001001" =>
if (wb_we_i = '1') then
tdc_desh4_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desh4_int;
end if;
rddata_reg(31 downto 0) <= tdc_desh4_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001010" =>
if (wb_we_i = '1') then
tdc_desl4_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desl4_int;
end if;
rddata_reg(31 downto 0) <= tdc_desl4_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001011" =>
if (wb_we_i = '1') then
tdc_desh5_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desh5_int;
end if;
rddata_reg(31 downto 0) <= tdc_desh5_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001100" =>
if (wb_we_i = '1') then
tdc_desl5_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desl5_int;
end if;
rddata_reg(31 downto 0) <= tdc_desl5_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001101" =>
if (wb_we_i = '1') then
tdc_desh6_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desh6_int;
end if;
rddata_reg(31 downto 0) <= tdc_desh6_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001110" =>
if (wb_we_i = '1') then
tdc_desl6_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desl6_int;
end if;
rddata_reg(31 downto 0) <= tdc_desl6_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001111" =>
if (wb_we_i = '1') then
tdc_desh7_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desh7_int;
end if;
rddata_reg(31 downto 0) <= tdc_desh7_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010000" =>
if (wb_we_i = '1') then
tdc_desl7_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= tdc_desl7_int;
end if;
rddata_reg(31 downto 0) <= tdc_desl7_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010001" =>
if (wb_we_i = '1') then
else
end if;
rddata_reg(7 downto 0) <= tdc_pol_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
......@@ -461,183 +438,156 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_raw0_i;
end if;
rddata_reg(31 downto 0) <= tdc_raw0_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesh0_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesh0_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010100" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesl0_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesl0_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_raw1_i;
end if;
rddata_reg(31 downto 0) <= tdc_raw1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesh1_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesh1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010111" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesl1_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesl1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_raw2_i;
end if;
rddata_reg(31 downto 0) <= tdc_raw2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesh2_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesh2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesl2_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesl2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_raw3_i;
end if;
rddata_reg(31 downto 0) <= tdc_raw3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011100" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesh3_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesh3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesl3_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesl3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_raw4_i;
end if;
rddata_reg(31 downto 0) <= tdc_raw4_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011111" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesh4_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesh4_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesl4_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesl4_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_raw5_i;
end if;
rddata_reg(31 downto 0) <= tdc_raw5_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesh5_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesh5_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesl5_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesl5_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100100" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_raw6_i;
end if;
rddata_reg(31 downto 0) <= tdc_raw6_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesh6_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesh6_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesl6_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesl6_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100111" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_raw7_i;
end if;
rddata_reg(31 downto 0) <= tdc_raw7_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesh7_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesh7_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_mesl7_i;
end if;
rddata_reg(31 downto 0) <= tdc_mesl7_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101010" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
tdc_dctl_req_int <= wrdata_reg(0);
rddata_reg(1) <= 'X';
else
end if;
rddata_reg(0) <= tdc_dctl_req_int;
rddata_reg(1) <= tdc_dctl_ack_i;
rddata_reg(2) <= 'X';
......@@ -670,16 +620,13 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101011" =>
if (wb_we_i = '1') then
tdc_csel_next_int <= wrdata_reg(0);
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
else
rddata_reg(0) <= 'X';
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= tdc_csel_last_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
......@@ -711,14 +658,12 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "101100" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
tdc_cal_int <= wrdata_reg(0);
else
end if;
rddata_reg(0) <= tdc_cal_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -751,13 +696,12 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101101" =>
if (wb_we_i = '1') then
tdc_luta_int <= wrdata_reg(15 downto 0);
else
end if;
rddata_reg(15 downto 0) <= tdc_luta_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
......@@ -775,20 +719,18 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_lutd_i;
end if;
rddata_reg(31 downto 0) <= tdc_lutd_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101111" =>
if (wb_we_i = '1') then
tdc_hisa_int <= wrdata_reg(15 downto 0);
else
end if;
rddata_reg(15 downto 0) <= tdc_hisa_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
......@@ -806,23 +748,19 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "110000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_hisd_i;
end if;
rddata_reg(31 downto 0) <= tdc_hisd_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "110001" =>
if (wb_we_i = '1') then
tdc_fcc_st_int <= wrdata_reg(0);
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
else
rddata_reg(0) <= 'X';
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= tdc_fcc_rdy_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
......@@ -854,27 +792,24 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "110010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_fcr_i;
end if;
rddata_reg(31 downto 0) <= tdc_fcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "110011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_fcsr_i;
end if;
rddata_reg(31 downto 0) <= tdc_fcsr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "111000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
else
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -907,13 +842,12 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "111001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
else
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -946,12 +880,11 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "111010" =>
if (wb_we_i = '1') then
else
end if;
rddata_reg(9 downto 0) <= eic_imr_int(9 downto 0);
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
......@@ -975,13 +908,12 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "111011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
else
end if;
rddata_reg(9 downto 0) <= eic_isr_status_int(9 downto 0);
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
......@@ -1005,7 +937,6 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
......@@ -1020,14 +951,14 @@ begin
-- Drive the data output bus
wb_data_o <= rddata_reg;
wb_dat_o <= rddata_reg;
-- Reset
process (bus_clock_int, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tdc_cs_rst_dly0 <= '0';
tdc_cs_rst_o <= '0';
elsif rising_edge(bus_clock_int) then
elsif rising_edge(clk_sys_i) then
tdc_cs_rst_dly0 <= tdc_cs_rst_int;
tdc_cs_rst_o <= tdc_cs_rst_int and (not tdc_cs_rst_dly0);
end if;
......@@ -1096,12 +1027,12 @@ begin
tdc_dctl_req_o <= tdc_dctl_req_int;
-- Freeze acknowledgement
-- Switch to next channel
process (bus_clock_int, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tdc_csel_next_dly0 <= '0';
tdc_csel_next_o <= '0';
elsif rising_edge(bus_clock_int) then
elsif rising_edge(clk_sys_i) then
tdc_csel_next_dly0 <= tdc_csel_next_int;
tdc_csel_next_o <= tdc_csel_next_int and (not tdc_csel_next_dly0);
end if;
......@@ -1118,12 +1049,12 @@ begin
tdc_hisa_o <= tdc_hisa_int;
-- Data
-- Measurement start
process (bus_clock_int, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tdc_fcc_st_dly0 <= '0';
tdc_fcc_st_o <= '0';
elsif rising_edge(bus_clock_int) then
elsif rising_edge(clk_sys_i) then
tdc_fcc_st_dly0 <= tdc_fcc_st_int;
tdc_fcc_st_o <= tdc_fcc_st_int and (not tdc_fcc_st_dly0);
end if;
......@@ -1177,7 +1108,7 @@ begin
g_irq1f_mode => 0
)
port map (
clk_i => bus_clock_int,
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int,
irq_ack_o => eic_irq_ack_int,
......@@ -1189,7 +1120,7 @@ begin
reg_isr_o => eic_isr_status_int,
reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_irq_o
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_ie0_i;
......@@ -1202,7 +1133,10 @@ begin
irq_inputs_vector_int(7) <= irq_ie7_i;
irq_inputs_vector_int(8) <= irq_isc_i;
irq_inputs_vector_int(9) <= irq_icc_i;
rwaddr_reg <= wb_addr_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
rtl/tdc_wbgen2_pkg.vhd 0 → 100644
View file @ 6896864b
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC
---------------------------------------------------------------------------------------
-- File : tdc_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from tdc_channel_wb.wb
-- Created : Tue Sep 11 22:15:48 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc_channel_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package tdc_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_tdc_in_registers is record
csr_rdy_i : std_logic;
csr_valid_i : std_logic;
raw_csr_valid_i : std_logic;
raw_taps_i : std_logic_vector(31 downto 0);
lutd_i : std_logic_vector(31 downto 0);
fcr_i : std_logic_vector(31 downto 0);
fcsr_i : std_logic_vector(31 downto 0);
end record;
constant c_tdc_in_registers_init_value: t_tdc_in_registers := (
csr_rdy_i => '0',
csr_valid_i => '0',
raw_csr_valid_i => '0',
raw_taps_i => (others => '0'),
lutd_i => (others => '0'),
fcr_i => (others => '0'),
fcsr_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_tdc_out_registers is record
csr_rst_o : std_logic;
csr_ro_en_o : std_logic;
calr_cal_mode_o : std_logic;
calr_cal_step_o : std_logic_vector(14 downto 0);
calr_cal_offset_o : std_logic_vector(14 downto 0);
raw_csr_ack_o : std_logic;
raw_bank_o : std_logic_vector(7 downto 0);
luta_o : std_logic_vector(15 downto 0);
end record;
constant c_tdc_out_registers_init_value: t_tdc_out_registers := (
csr_rst_o => '0',
csr_ro_en_o => '0',
calr_cal_mode_o => '0',
calr_cal_step_o => (others => '0'),
calr_cal_offset_o => (others => '0'),
raw_csr_ack_o => '0',
raw_bank_o => (others => '0'),
luta_o => (others => '0')
);
function "or" (left, right: t_tdc_in_registers) return t_tdc_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component tdc_channel_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_tdc_in_registers;
regs_o : out t_tdc_out_registers
);
end component;
end package;
package body tdc_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_tdc_in_registers) return t_tdc_in_registers is
variable tmp: t_tdc_in_registers;
begin
tmp.csr_rdy_i := f_x_to_zero(left.csr_rdy_i) or f_x_to_zero(right.csr_rdy_i);
tmp.csr_valid_i := f_x_to_zero(left.csr_valid_i) or f_x_to_zero(right.csr_valid_i);
tmp.raw_csr_valid_i := f_x_to_zero(left.raw_csr_valid_i) or f_x_to_zero(right.raw_csr_valid_i);
tmp.raw_taps_i := f_x_to_zero(left.raw_taps_i) or f_x_to_zero(right.raw_taps_i);
tmp.lutd_i := f_x_to_zero(left.lutd_i) or f_x_to_zero(right.lutd_i);
tmp.fcr_i := f_x_to_zero(left.fcr_i) or f_x_to_zero(right.fcr_i);
tmp.fcsr_i := f_x_to_zero(left.fcsr_i) or f_x_to_zero(right.fcsr_i);
return tmp;
end function;
end package body;
rtl/xwb_urv_mcs.vhd 0 → 100644
View file @ 6896864b
-------------------------------------------------------------------------------
-- Title : LM32 Embedded Microcontroller System (MCS)
-- Project : General Cores Library
-------------------------------------------------------------------------------
-- File : xwb_lm32_mcs.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- A small embedded microcontroller with some amount of RAM,
-- UART and a Wishbone bus for user peripherals. The code can be preloaded
-- or loaded on-the-fly throufh the Wishbone system bus.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014-2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
entity xwb_urv_mcs is
generic(
-- size of the code/data memory in bytes
g_iram_size : integer := 65536;
-- timeout (in clock cycles) for the Wishbone master.
-- exceeding the timeout (e.g. due to an incorrect address/
-- unresponsive slave) causes a WB error after g_bus_timeout cycles.
g_bus_timeout : integer := 30;
-- file (.bram format) with the firmware to pre-load during synthesis.
g_preload_firmware : string := "";
-- Enable host interface (allows loading code from a system bus)
g_with_host_if : boolean := true
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
irq_i : in std_logic_vector(31 downto 0) := x"00000000";
host_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
host_wb_o : out t_wishbone_slave_out;
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in
);
end xwb_urv_mcs;
architecture wrapper of xwb_urv_mcs is
constant c_address_bits : integer := 20;
function f_x_to_zero (x : std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector(x'length-1 downto 0);
begin
-- synthesis translate_off
for i in 0 to x'length-1 loop
if(x(i) = '1') then
tmp(i) := '1';
else
tmp(i) := '0';
end if;
end loop;
return tmp;
-- synthesis translate_on
return x;
end function;
constant c_iram_addr_width : integer := f_log2_size(g_iram_size)-2;
signal cpu_reset, cpu_enable, cpu_reset_d : std_logic;
signal bus_timeout : unsigned(7 downto 0);
signal bus_timeout_hit : std_logic;
signal im_addr : std_logic_vector(31 downto 0);
signal im_data : std_logic_vector(31 downto 0);
signal im_valid : std_logic;
signal ha_im_addr : std_logic_vector(c_address_bits-1 downto 0);
signal ha_im_wdata, ha_im_rdata : std_logic_vector(31 downto 0);
signal ha_im_access, ha_im_write : std_logic;
signal im_addr_muxed : std_logic_vector(c_address_bits-1 downto 0);
signal dm_addr, dm_data_s, dm_data_l : std_logic_vector(31 downto 0);
signal dm_data_select : std_logic_vector(3 downto 0);
signal dm_load, dm_store, dm_load_done, dm_store_done, dm_ready : std_logic;
signal dm_cycle_in_progress, dm_is_wishbone : std_logic;
signal dm_mem_rdata, dm_wb_rdata : std_logic_vector(31 downto 0);
signal dm_wb_write, dm_select_wb : std_logic;
signal dm_data_write : std_logic;
signal cpu_csr_udata_out, cpu_csr_uaddr_addr, cpu_csr_udata_in : std_logic_vector(31 downto 0);
signal cpu_csr_udata_load : std_logic;
signal iram_bwe : std_logic_vector(3 downto 0);
function f_resize ( x :std_logic_vector; n : integer ) return std_logic_vector is
variable rv : std_logic_vector(n-1 downto 0);
begin
rv := (others => '0');
rv (x'length-1 downto 0) := x;
return rv;
end f_resize;
signal cpu_dwb_out : t_wishbone_master_out;
signal cpu_dwb_in : t_wishbone_master_in;
begin
dm_is_wishbone <= dm_addr(c_address_bits-1);
-- Wishbone bus arbitration / internal RAM access
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(rst_n_i = '0') then
cpu_dwb_out.cyc <= '0';
dm_cycle_in_progress <= '0';
dm_load_done <= '0';
dm_store_done <= '0';
dm_select_wb <= '0';
bus_timeout <= (others => '0');
else
if(dm_cycle_in_progress = '0') then -- access to internal memory
bus_timeout <= (others => '0');
if(dm_is_wishbone = '0') then
if(dm_store = '1') then
dm_load_done <= '0';
dm_store_done <= '1';
dm_select_wb <= '0';
elsif (dm_load = '1') then
dm_load_done <= '1';
dm_store_done <= '0';
dm_select_wb <= '0';
else
dm_store_done <= '0';
dm_load_done <= '0';
dm_select_wb <= '0';
end if;
else
if(dm_load = '1' or dm_store = '1') then
cpu_dwb_out.cyc <= '1';
cpu_dwb_out.stb <= '1';
cpu_dwb_out.we <= dm_store;
dm_wb_write <= dm_store;
cpu_dwb_out.adr <= dm_addr;
cpu_dwb_out.dat <= dm_data_s;
cpu_dwb_out.sel <= dm_data_select;
dm_load_done <= '0';
dm_store_done <= '0';
dm_cycle_in_progress <= '1';
else
dm_store_done <= '0';
dm_load_done <= '0';
dm_cycle_in_progress <= '0';
end if;
end if;
else -- dm_cycle_in_progress = 1
bus_timeout <= bus_timeout + 1;
if(cpu_dwb_in.stall = '0') then
cpu_dwb_out.stb <= '0';
end if;
if(cpu_dwb_in.ack = '1' or bus_timeout = g_bus_timeout) then
if(dm_wb_write = '0') then
dm_wb_rdata <= cpu_dwb_in.dat;
dm_select_wb <= '1';
dm_load_done <= '1';
else
dm_store_done <= '1';
dm_select_wb <= '0';
end if;
dm_cycle_in_progress <= '0';
cpu_dwb_out.cyc <= '0';
end if;
end if;
end if;
end if;
end process;
dm_data_l <= dm_wb_rdata when dm_select_wb = '1' else dm_mem_rdata;
im_addr_muxed <= ha_im_addr when ha_im_access = '1' else im_addr(c_address_bits-1 downto 0);
dm_ready <= '1';
U_CPU_core : entity work.urv_cpu
port map (
clk_i => clk_sys_i,
rst_i => cpu_reset,
irq_i => irq_i(0),
im_addr_o => im_addr,
im_data_i => im_data,
im_valid_i => im_valid,
dm_addr_o => dm_addr,
dm_data_s_o => dm_data_s,
dm_data_l_i => dm_data_l,
dm_data_select_o => dm_data_select,
dm_ready_i => dm_ready,
dm_store_o => dm_store,
dm_load_o => dm_load,
dm_load_done_i => dm_load_done,
dm_store_done_i => dm_store_done,
dbg_force_i => '0',
dbg_insn_i => x"00000000",
dbg_mbx_data_i => x"00000000",
dbg_mbx_write_i => '0',
dbg_insn_set_i => '0',
dbg_tx_ready_i => '0',
dbg_rx_data_i => x"00",
dbg_rx_valid_i => '0' );
dm_data_write <= not dm_is_wishbone and dm_store;
gen_iram_blocks : for i in 0 to 3 generate
iram : generic_dpram
generic map (
g_data_width => 8,
g_size => g_iram_size / 4,
g_with_byte_enable => false,
g_dual_clock => false,
g_addr_conflict_resolution => "dont_care")
port map (
rst_n_i => rst_n_i,
clka_i => clk_sys_i,
wea_i => ha_im_write,
aa_i => im_addr_muxed(f_log2_size(g_iram_size)-1 downto 2),
da_i => ha_im_wdata(8*i+7 downto 8*i),
qa_o => im_data(8*i+7 downto 8*i),
clkb_i => clk_sys_i,
web_i => iram_bwe(i),
ab_i => dm_addr(f_log2_size(g_iram_size)-1 downto 2),
db_i => dm_data_s(8*i+7 downto 8*i),
qb_o => dm_mem_rdata(8*i+7 downto 8*i)
);
iram_bwe(i) <= dm_data_select(i) and dm_data_write;
end generate gen_iram_blocks;
-- U_iram : entity work.urv_iram
-- generic map (
-- g_size => g_iram_size,
-- g_init_file => g_preload_firmware,
-- g_simulation => 0)
-- port map (
-- clk_i => clk_sys_i,
-- ena_i => '1',
-- wea_i => ha_im_write,
-- bwea_i => "1111",
-- aa_i => x"deadbeef", --x"000" & im_addr_muxed,
-- da_i => ha_im_wdata,
-- qa_o => im_data,
-- enb_i => '1',
-- bweb_i => dm_data_select,
-- web_i => dm_data_write,
-- ab_i => dm_addr,
-- db_i => dm_data_s,
-- qb_o => dm_mem_rdata
-- );
ha_im_rdata <= im_data;
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(cpu_reset = '1') then
im_valid <= '0';
cpu_reset_d <= '1';
else
cpu_reset_d <= cpu_reset;
im_valid <= not ha_im_access and (not cpu_reset_d);
end if;
end if;
end process;
dwb_o <= cpu_dwb_out;
cpu_dwb_in.dat <= f_x_to_zero(dwb_i.dat);
cpu_dwb_in.ack <= dwb_i.ack;
cpu_dwb_in.err <= dwb_i.err;
cpu_dwb_in.rty <= dwb_i.rty;
cpu_dwb_in.stall <= dwb_i.stall;
cpu_reset <= not rst_n_i or (not cpu_enable);
ha_im_access <= not cpu_enable;
p_local_regs : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
cpu_enable <= '0';
host_wb_o.ack <= '0';
host_wb_o.err <= '0';
host_wb_o.rty <= '0';
host_wb_o.stall <= '0';
else
ha_im_write <= '0';
host_wb_o.ack <= '0';
if host_wb_i.cyc = '1' and host_wb_i.stb = '1' then
host_wb_o.ack <= '1';
if host_wb_i.we = '1' then
case host_wb_i.adr(3 downto 0) is
when "0000" => -- csr
cpu_enable <= host_wb_i.dat(0);
when "0100" => -- data
ha_im_wdata <= host_wb_i.dat;
ha_im_write <= '1';
when "1000" => -- addr
ha_im_addr <= host_wb_i.dat(c_address_bits-3 downto 0) & "00" ;
when others => null;
end case;
else
case host_wb_i.adr(3 downto 0) is
when "0000" =>
host_wb_o.dat(0) <= cpu_enable;
host_wb_o.dat(31 downto 1) <= std_logic_vector(to_unsigned(g_iram_size, 31));
when "0100" =>
host_wb_o.dat <= ha_im_rdata;
when others => null;
end case;
end if;
end if;
end if;
end if;
end process;
end wrapper;
sw/arch/urv/crt0.S 0 → 100644
View file @ 6896864b
.section .boot, "ax", @progbits
.global _start
_start:
j _entry
.org 0x8
.extern trap_entry
_exception_entry:
j trap_entry
_entry:
la gp, _gp /* Initialize global pointer */
la sp, _fstack
la t0, _fexception_stack
csrrw t0, mscratch, t0
/* clear the bss segment */
la t0, _fbss
la t1, _end
1:
#ifdef __riscv64
sd zero,0(t0)
addi t0, t0, 8
#else
sw zero,0(t0)
addi t0, t0, 4
#endif
bltu t0, t1, 1b
call main
1:
j 1b
sw/arch/urv/emulate.c 0 → 100644
View file @ 6896864b
#include <stdint.h>
struct rv_trap_context {
uint32_t r[32];
uint32_t mstatus;
uint32_t mepc;
uint32_t mbadaddr;
uint32_t mcause;
};
void undefined_insn_handler( struct rv_trap_context *ctx )
{
uint32_t insn = *(volatile uint32_t *)( ctx->mepc );
ctx->r[0] = 0;
uint32_t rs1 = ctx->r[(insn >> 15) & 0x1f];
uint32_t rs2 = ctx->r[(insn >> 20) & 0x1f];
uint32_t rdi = (insn >> 7) & 0x1f;
// we support MUL natively
if ( (insn & 0xfe00707f) == 0x2001033 ) // MULH
ctx->r[rdi] = ( (int64_t)(int32_t)rs1 * (int64_t)(int32_t) rs2) >> 32;
else if ( (insn & 0xfe00707f) == 0x2002033 ) // MULHSU
ctx->r[rdi] = ((int64_t)(int32_t)rs1 * (uint64_t) rs2) >> 32;
else if ( (insn & 0xfe00707f) == 0x2003033 ) // MULHU
ctx->r[rdi] = ((uint64_t) rs1 * (uint64_t) rs2) >> 32;
else if ( (insn & 0xfe00707f) == 0x2004033 ) // DIV
ctx->r[rdi] = (int32_t)rs1 / (int32_t) rs2;
else if ( (insn & 0xfe00707f) == 0x2005033 ) // DIVU
ctx->r[rdi] = (uint32_t)rs1 / (uint32_t) rs2;
else if ( (insn & 0xfe00707f) == 0x2006033 ) // REM
ctx->r[rdi] = (int32_t)rs1 % (int32_t) rs2;
else if ( (insn & 0xfe00707f) == 0x2007033 ) // REMU
ctx->r[rdi] = (uint32_t)rs1 % (uint32_t) rs2;
ctx->mepc += 4;
asm volatile ("csrc mip, 0x4"); // clear exception
}
\ No newline at end of file
sw/arch/urv/irq.S 0 → 100644
View file @ 6896864b
.section .text
.global trap_entry
trap_entry:
csrrw sp,mscratch,sp
addi sp,sp,-320
sw ra,4(sp)
sw gp,12(sp)
sw tp,16(sp)
sw t0,20(sp)
sw t1,24(sp)
sw t2,28(sp)
sw s0,32(sp)
sw s1,36(sp)
sw a0,40(sp)
sw a1,44(sp)
sw a2,48(sp)
sw a3,52(sp)
sw a4,56(sp)
sw a5,60(sp)
sw a6,64(sp)
sw a7,68(sp)
sw s2,72(sp)
sw s3,76(sp)
sw s4,80(sp)
sw s5,84(sp)
sw s6,88(sp)
sw s7,92(sp)
sw s8,96(sp)
sw s9,100(sp)
sw s10,104(sp)
sw s11,108(sp)
sw t3,112(sp)
sw t4,116(sp)
sw t5,120(sp)
sw t6,124(sp)
csrr t0,mscratch
csrr s0,mstatus
csrr t1,mepc
csrr t2,mbadaddr
csrr t3,mcause
sw t0,8(sp)
sw s0,128(sp)
sw t1,132(sp)
sw t2,136(sp)
sw t3,140(sp)
li t0,-1
sw t0,144(sp)
mv a0,sp
la t0, jump_table
sll t3, t3, 2
add t0, t0, t3
lw t0, 0(t0)
la ra, jump_table_return
jr t0
jump_table:
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
jump_table_return:
mv a0,sp
lw t1,128(a0)
lw t2,132(a0)
addi sp,sp,320
csrw mscratch,sp
csrw mepc,t2
lw ra,4(a0)
lw sp,8(a0)
lw gp,12(a0)
lw tp,16(a0)
lw t0,20(a0)
lw t1,24(a0)
lw t2,28(a0)
lw s0,32(a0)
lw s1,36(a0)
lw a1,44(a0)
lw a2,48(a0)
lw a3,52(a0)
lw a4,56(a0)
lw a5,60(a0)
lw a6,64(a0)
lw a7,68(a0)
lw s2,72(a0)
lw s3,76(a0)
lw s4,80(a0)
lw s5,84(a0)
lw s6,88(a0)
lw s7,92(a0)
lw s8,96(a0)
lw s9,100(a0)
lw s10,104(a0)
lw s11,108(a0)
lw t3,112(a0)
lw t4,116(a0)
lw t5,120(a0)
lw t6,124(a0)
lw a0,40(a0)
mret
.weak undefined_handler
undefined_handler:
j undefined_handler
sw/arch/urv/riscv.h 0 → 100644
View file @ 6896864b
#ifndef __RISCV_H
#define __RISCV_H
#ifdef __GNUC__
#define riscv_read_csr(reg) ({ unsigned long __tmp; \
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
__tmp; })
#define riscv_write_csr(reg, val) \
asm volatile ("csrw " #reg ", %0" :: "r"(val))
#define riscv_swap_csr(reg, val) ({ long __tmp; \
asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
__tmp; })
#define riscv_set_csr(reg, bit) ({ unsigned long __tmp; \
if (__builtin_constant_p(bit) && (bit) < 32) \
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
else \
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
__tmp; })
#define riscv_clear_csr(reg, bit) ({ unsigned long __tmp; \
if (__builtin_constant_p(bit) && (bit) < 32) \
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
else \
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
__tmp; })
#define riscv_rdtime() riscv_read_csr(time)
#define riscv_rdcycle() riscv_read_csr(cycle)
#define riscv_rdinstret() riscv_read_csr(instret)
#endif
#endif
sw/arch/urv/urv.ld 0 → 100644
View file @ 6896864b
OUTPUT_FORMAT("elf32-littleriscv")
ENTRY(_start)
MEMORY
{
ram :
ORIGIN = 0x00000000,
LENGTH = 32768 - 2048
stack :
ORIGIN = 32768 - 2048,
LENGTH = 2048
smem :
ORIGIN = 0x40200000,
LENGTH = 65536
}
SECTIONS
{
/*--------------------------------------------------------------------*/
/* Code and read-only segment */
/*--------------------------------------------------------------------*/
/* Begining of code and text segment */
. = 0x00000000;
_ftext = .;
PROVIDE( eprol = . );
/* text: Program code section */
.text :
{
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
} > ram
/* init: Code to execute before main (called by crt0.S) */
.init :
{
KEEP( *(.init) )
} > ram
/* fini: Code to execute after main (called by crt0.S) */
.fini :
{
KEEP( *(.fini) )
} > ram
/* rodata: Read-only data */
.rodata :
{
*(.rdata)
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
} > ram
/* End of code and read-only segment */
PROVIDE( etext = . );
_etext = .;
/*--------------------------------------------------------------------*/
/* Global constructor/destructor segement */
/*--------------------------------------------------------------------*/
/* The .ctors/.dtors sections are special sections which contain a
list of constructor/destructor function pointers. crtbegin.o
includes code in a .init section which goes through the .ctors list
and calls each constuctor. crtend.o includes code in a .fini
section which goes through the .dtors list and calls each
destructor. crtbegin.o includes a special null pointer in its own
.ctors/.dtors sections which acts as a start indicator for those
lists. crtend.o also includes a special null pointer in its own
.ctors/.dtors sections which acts as an end indictor. The linker
commands below are setup so that crtbegin.o's .ctors/.dtors
sections are always first and crtend.o's .ctors/.dtors sections are
always last. This is the only way the list of functions will have
the begin and end indicators in the right place. */
/* ctors : Array of global constructor function pointers */
/*--------------------------------------------------------------------*/
/* Initialized data segment */
/*--------------------------------------------------------------------*/
/* Start of initialized data segment */
. = ALIGN(16);
_fdata = .;
/* data: Writable data */
.data :
{
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
} > ram
/* End of initialized data segment */
PROVIDE( edata = . );
_edata = .;
/* Have _gp point to middle of sdata/sbss to maximize displacement range */
. = ALIGN(16);
_gp = . + 0x800;
/* Writable small data segment */
.sdata :
{
*(.sdata)
*(.sdata.*)
*(.srodata.*)
*(.gnu.linkonce.s.*)
} > ram
/*--------------------------------------------------------------------*/
/* Uninitialized data segment */
/*--------------------------------------------------------------------*/
/* Start of uninitialized data segment */
. = ALIGN(8);
_fbss = .;
/* Writable uninitialized small data segment */
.sbss :
{
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
} > ram
/* bss: Uninitialized writeable data section */
. = .;
_bss_start = .;
.bss :
{
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
} > ram
/* End of uninitialized data segment (used by syscalls.c for heap) */
PROVIDE( end = . );
_end = ALIGN(8);
.smem : { *(.smem) } > smem
PROVIDE(_endram = ORIGIN(stack));
PROVIDE(_fexception_stack = ORIGIN(stack) + LENGTH(stack) - 4);
PROVIDE(_fstack = ORIGIN(stack) + LENGTH(stack) - 4 - 0x400 );
}
sw/arch/urv/urv.mk 0 → 100644
View file @ 6896864b
# and don't touch the rest unless you know what you're doing.
CROSS_COMPILE ?= riscv32-elf-
CC = $(CROSS_COMPILE)gcc
LD = $(CROSS_COMPILE)ld
OBJDUMP = $(CROSS_COMPILE)objdump
OBJCOPY = $(CROSS_COMPILE)objcopy
SIZE = $(CROSS_COMPILE)size
CFLAGS = -g -O2 -I. -I../common -I../../include -I../include/ -mabi=ilp32 -march=rv32im -ffunction-sections -fdata-sections
OBJS += ../arch/urv/crt0.o ../arch/urv/irq.o ../arch/urv/emulate.o ../common/printf.o ../common/vsprintf-xint.o ../common/board.o ../common/uart.o
LDSCRIPT = ../arch/urv/urv.ld
LDFLAGS = -Wl,--gc-sections
$(OUTPUT): $(LDSCRIPT) $(OBJS)
${CC} ${CFLAGS} ${LDFLAGS} -g -o $(OUTPUT).elf -nostartfiles $(OBJS) -T $(LDSCRIPT) -lgcc -lc
${OBJCOPY} --remove-section .smem -O binary $(OUTPUT).elf $(OUTPUT).bin
${OBJDUMP} -S $(OUTPUT).elf > disasm.S
# ../common/genraminit $(OUTPUT).bin > $(OUTPUT).ram
$(SIZE) $(OUTPUT).elf
../arch/urv/emulate.o: ../arch/urv/emulate.c
${CC} -O2 -mabi=ilp32 -march=rv32i -c $^ -o $@ -I.
%.o: %.S
${CC} -mabi=ilp32 -march=rv32i -c $^ -o $@
clean:
rm -f $(OBJS) $(OUTPUT).bin
\ No newline at end of file
sw/common/board.c 0 → 100644
View file @ 6896864b
#include "board.h"
#include "uart.h"
void board_init()
{
uart_init_hw();
}
\ No newline at end of file
sw/common/board.h 0 → 100644
View file @ 6896864b
#ifndef __BOARD_H
#define __BOARD_H
#include <stdint.h>
#define SYSTEM_CLOCK_FREQ 62500000
#define UART_BAUDRATE (SYSTEM_CLOCK_FREQ/2)
#define BASE_UART (void *) 0x00081000
static inline uint32_t board_system_freq()
{
return SYSTEM_CLOCK_FREQ;
}
static inline void usleep(int us)
{
int t = us * board_system_freq() / 5000000;
while(t--) asm volatile("nop");
}
static inline uint32_t readl(uint32_t addr)
{
return *(volatile uint32_t *)(addr);
}
static inline void writel(uint32_t data, uint32_t addr)
{
*(volatile uint32_t *)(addr) = data;
}
#endif
sw/common/gpio.c 0 → 100644
View file @ 6896864b
#include "board.h"
#include "gpio.h"
#define GPIO_REG_COR 0
#define GPIO_REG_SOR 4
#define GPIO_REG_DDR 8
#define GPIO_REG_PSR 12
#define GPIO_BANK_SIZE 32
static void wb_gpio_set_dir(const struct gpio_pin *pin, int dir)
{
void *base = (void*)pin->rwops->priv;
volatile uint32_t *dr = base + (GPIO_BANK_SIZE * (pin->pin >> 5)) + GPIO_REG_DDR;
uint32_t mask = 1 << (pin->pin & 0x1f);
if (dir)
*dr |= mask;
else
*dr &= ~mask;
}
static void wb_gpio_out(const struct gpio_pin *pin, int value)
{
void *base = (void*)pin->rwops->priv;
volatile void *regs = base + (GPIO_BANK_SIZE * (pin->pin >> 5));
uint32_t mask = 1 << (pin->pin & 0x1f);
if(value)
*(volatile uint32_t *)(regs + GPIO_REG_SOR) = mask;
else
*(volatile uint32_t *)(regs + GPIO_REG_COR) = mask;
}
static int wb_gpio_in(const struct gpio_pin *pin)
{
void *base = (void*)pin->rwops->priv;
volatile uint32_t *psr = base + (GPIO_BANK_SIZE * (pin->pin >> 5)) + GPIO_REG_PSR;
uint32_t mask = 1 << (pin->pin & 0x1f);
return (*psr & mask) ? 1 : 0;
}
struct gpio_rwops gpio_main = {
BASE_GPIO,
wb_gpio_set_dir,
wb_gpio_out,
wb_gpio_in
};
sw/common/gpio.h 0 → 100644
View file @ 6896864b
#ifndef __GPIO_H
#define __GPIO_H
#include "board.h"
struct gpio_pin;
typedef void (*set_dir_func)(const struct gpio_pin *, int);
typedef void (*set_out_func)(const struct gpio_pin *, int);
typedef int (*read_pin_func)(const struct gpio_pin *);
struct gpio_rwops
{
void* priv;
set_dir_func set_dir;
set_out_func set_out;
read_pin_func read_pin;
};
struct gpio_pin
{
const struct gpio_rwops *rwops;
int pin;
};
extern struct gpio_rwops gpio_main;
extern struct gpio_rwops gpio_rtm;
static inline void gpio_set_dir(const struct gpio_pin *pin, int dir)
{
pin->rwops->set_dir(pin, dir);
}
static inline void gpio_out(const struct gpio_pin *pin, int value)
{
pin->rwops->set_out(pin, value);
}
static inline int gpio_in(const struct gpio_pin *pin)
{
return pin->rwops->read_pin(pin);
}
static const struct gpio_pin gpio_pin_clk_muxab_sel0 = { &gpio_main, 23 };
static const struct gpio_pin gpio_pin_clk_muxab_sel1 = { &gpio_main, 24 };
static const struct gpio_pin gpio_pin_clk_mux1a_sel0 = { &gpio_main, 25 };
static const struct gpio_pin gpio_pin_clk_mux1a_sel1 = { &gpio_main, 26 };
static const struct gpio_pin gpio_pin_clk_mux1b_sel0 = { &gpio_main, 27 };
static const struct gpio_pin gpio_pin_clk_mux1b_sel1 = { &gpio_main, 28 };
static const struct gpio_pin gpio_pin_clk_mux2a_sel0 = { &gpio_main, 29 };
static const struct gpio_pin gpio_pin_clk_mux2a_sel1 = { &gpio_main, 30 };
static const struct gpio_pin gpio_pin_clk_mux2b_sel0 = { &gpio_main, 32 };
static const struct gpio_pin gpio_pin_clk_mux2b_sel1 = { &gpio_main, 33 };
static const struct gpio_pin gpio_pin_clk_mux_dac_sel0 = { &gpio_main, 57 };
static const struct gpio_pin gpio_pin_clk_mux_dac_sel1 = { &gpio_main, 58 };
static const struct gpio_pin gpio_pin_si_rst_n = { &gpio_main, 16 };
static const struct gpio_pin gpio_pin_si_spi_sclk = { &gpio_main, 20 };
static const struct gpio_pin gpio_pin_si_spi_di = { &gpio_main, 21 };
static const struct gpio_pin gpio_pin_si_spi_do = { &gpio_main, 22 }; // Si3
static const struct gpio_pin gpio_pin_si_spi_cs_n1 = { &gpio_main, 19 };
static const struct gpio_pin gpio_pin_div_spi_sclk = { &gpio_main, 34 };
static const struct gpio_pin gpio_pin_div_spi_dio = { &gpio_main, 35 };
static const struct gpio_pin gpio_pin_div_spi_cs_n1 = { &gpio_main, 36 };
static const struct gpio_pin gpio_pin_div_spi_cs_n2 = { &gpio_main, 37 };
static const struct gpio_pin gpio_pin_div_function = { &gpio_main, 40 };
static const struct gpio_pin gpio_pin_adc_sync = { &gpio_main, 41};
static const struct gpio_pin gpio_pin_adc_oeb_l = { &gpio_main, 42};
static const struct gpio_pin gpio_pin_adc_pwdn = { &gpio_main, 43};
static const struct gpio_pin gpio_pin_adc_spi_cs_l1 = { &gpio_main, 45 };
static const struct gpio_pin gpio_pin_adc_spi_cs_l2 = { &gpio_main, 46 };
static const struct gpio_pin gpio_pin_adc_spi_cs_l3 = { &gpio_main, 47 };
static const struct gpio_pin gpio_pin_adc_spi_cs_l4 = { &gpio_main, 48 };
static const struct gpio_pin gpio_pin_adc_spi_cs_l5 = { &gpio_main, 49 };
static const struct gpio_pin gpio_pin_adc_spi_sclk = { &gpio_main, 50 };
static const struct gpio_pin gpio_pin_adc_spi_dio = { &gpio_main, 51 };
static const struct gpio_pin gpio_pin_rtm_usr_scl = { &gpio_main, 55 };
static const struct gpio_pin gpio_pin_rtm_usr_sda = { &gpio_main, 56 };
static const struct gpio_pin gpio_pin_leds[] =
{
{ &gpio_main, 0 },
{ &gpio_main, 1 },
{ &gpio_main, 2 },
{ &gpio_main, 3 },
{ &gpio_main, 4 },
{ &gpio_main, 5 },
{ &gpio_main, 6 },
{ &gpio_main, 7 },
{ &gpio_main, 8 },
{ &gpio_main, 9 },
{ &gpio_main, 10 },
{ &gpio_main, 11 },
{ &gpio_main, 12 },
{ &gpio_main, 13 },
{ &gpio_main, 14 },
{ &gpio_main, 15 }
};
#endif
sw/common/hw/wb_uart.h 0 → 100644
View file @ 6896864b
/*
Register definitions for slave core: Simple Wishbone UART
* File : ../../../../software/include/hw/wb_uart.h
* Author : auto-generated by wbgen2 from uart.wb
* Created : Mon Feb 21 22:25:02 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE uart.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_UART_WB
#define __WBGEN2_REGDEFS_UART_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Status Register */
/* definitions for field: TX busy in reg: Status Register */
#define UART_SR_TX_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX ready in reg: Status Register */
#define UART_SR_RX_RDY WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Baudrate control register */
/* definitions for register: Transmit data regsiter */
/* definitions for field: Transmit data in reg: Transmit data regsiter */
#define UART_TDR_TX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_TDR_TX_DATA_SHIFT 0
#define UART_TDR_TX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_TDR_TX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: Receive data regsiter */
/* definitions for field: Received data in reg: Receive data regsiter */
#define UART_RDR_RX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_RDR_RX_DATA_SHIFT 0
#define UART_RDR_RX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_RDR_RX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* [0x0]: REG Status Register */
#define UART_REG_SR 0x00000000
/* [0x4]: REG Baudrate control register */
#define UART_REG_BCR 0x00000004
/* [0x8]: REG Transmit data regsiter */
#define UART_REG_TDR 0x00000008
/* [0xc]: REG Receive data regsiter */
#define UART_REG_RDR 0x0000000c
PACKED struct UART_WB {
/* [0x0]: REG Status Register */
uint32_t SR;
/* [0x4]: REG Baudrate control register */
uint32_t BCR;
/* [0x8]: REG Transmit data regsiter */
uint32_t TDR;
/* [0xc]: REG Receive data regsiter */
uint32_t RDR;
};
#endif
sw/common/pp-printf.h 0 → 100644
View file @ 6896864b
/*
* This work is part of the White Rabbit Node Core project.
*
* Copyright (C) 2013-2014 CERN (www.cern.ch)
* Author: Alessandro Rubini <rubini@gnudd.com>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#ifndef __PP_PRINTF_H
#define __PP_PRINTF_H
#include <stdarg.h>
#define CONFIG_PRINT_BUFSIZE 128
extern int pp_printf(const char *fmt, ...)
__attribute__((format(printf,1,2)));
extern int pp_sprintf(char *s, const char *fmt, ...)
__attribute__((format(printf,2,3)));
extern int pp_vprintf(const char *fmt, va_list args);
extern int pp_vsprintf(char *buf, const char *, va_list)
__attribute__ ((format (printf, 2, 0)));
/* This is what we rely on for output */
extern int puts(const char *s);
#endif
sw/common/printf.c 0 → 100644
View file @ 6896864b
/*
* Basic printf based on vprintf based on vsprintf
*
* Alessandro Rubini for CERN, 2011 -- public domain
* (please note that the vsprintf is not public domain but GPL)
*/
#include <stdarg.h>
#include <pp-printf.h>
static char print_buf[CONFIG_PRINT_BUFSIZE];
int pp_vprintf(const char *fmt, va_list args)
{
int ret;
ret = pp_vsprintf(print_buf, fmt, args);
puts(print_buf);
return ret;
}
int pp_sprintf(char *s, const char *fmt, ...)
{
va_list args;
int ret;
va_start(args, fmt);
ret = pp_vsprintf(s, fmt, args);
va_end(args);
return ret;
}
int pp_printf(const char *fmt, ...)
{
va_list args;
int ret;
va_start(args, fmt);
ret = pp_vprintf(fmt, args);
va_end(args);
return ret;
}
sw/common/uart.c 0 → 100644
View file @ 6896864b
/*
* DSI Shield
*
* Copyright (C) 2013-2014 twl
*
* This program is free software: you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 3 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* uart.c - simple UART driver */
#include <stdint.h>
#include "uart.h"
#include "board.h"
#include <hw/wb_uart.h>
#define CALC_BAUD(baudrate) \
( ((( (unsigned int)baudrate << 12)) + \
(board_system_freq() >> 8)) / (board_system_freq() >> 7) )
volatile struct UART_WB *uart;
#ifdef SIMULATION
volatile uint32_t *TX_REG = 0x100000;
volatile uint32_t *RX_REG = 0x100004;
volatile uint32_t *STATUS_REG = 0x100008;
#endif
void uart_init_hw()
{
uart = (volatile struct UART_WB *)BASE_UART;
#ifndef SIMULATION
uart->BCR = CALC_BAUD(UART_BAUDRATE);
#else
// uart->BCR = CALC_BAUD((CPU_CLOCK/10));
#endif
}
void uart_write_byte(int b)
{
#ifndef SIMULATION
if (b == '\n')
uart_write_byte('\r');
while (uart->SR & UART_SR_TX_BUSY)
;
uart->TDR = b;
#else
*TX_REG = b;
#endif
}
int uart_poll()
{
#ifndef SIMULATION
return uart->SR & UART_SR_RX_RDY;
#else
return (*STATUS_REG) ? 1: 0;
#endif
}
int uart_read_byte()
{
if (!uart_poll())
return -1;
#ifndef SIMULATION
return uart->RDR & 0xff;
#else
return (*RX_REG) & 0xff;
#endif
}
int puts(const char *s)
{
char c;
while((c = *s++))
uart_write_byte(c);
return 0;
}
sw/common/uart.h 0 → 100644
View file @ 6896864b
/*
* DSI Shield
*
* Copyright (C) 2013-2014 twl
*
* This program is free software: you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 3 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __UART_H
#define __UART_H
void uart_init_sw(void);
void uart_init_hw(void);
void uart_write_byte(int b);
int uart_write_string(const char *s);
int puts(const char *s);
int uart_read_byte(void);
int uart_poll();
#endif
sw/common/vsprintf-xint.c 0 → 100644
View file @ 6896864b
/*
* vsprintf-xint: a possible free-software replacement for mprintf
*
* public domain
*/
#include <stdarg.h>
#include <stdint.h>
static const char hex[] = "0123456789abcdef";
static int number(char *out, unsigned value, int base, int lead, int wid)
{
char tmp[16];
int i = 16, ret, negative = 0;
/* No error checking at all: it is as ugly as possible */
if ((signed)value < 0 && base == 10) {
negative = 1;
value = -value;
}
while (value && i) {
tmp[--i] = hex[value % base];
value /= base;
}
if (i == 16)
tmp[--i] = '0';
if (negative && lead == ' ') {
tmp[--i] = '-';
negative = 0;
}
while (i > 16 - wid + negative)
tmp[--i] = lead;
if (negative)
tmp[--i] = '-';
ret = 16 - i;
while (i < 16)
*(out++) = tmp[i++];
return ret;
}
int pp_vsprintf(char *buf, const char *fmt, va_list args)
{
char *s, *str = buf;
int base, lead, wid;
for (; *fmt ; ++fmt) {
if (*fmt != '%') {
*str++ = *fmt;
continue;
}
base = 10;
lead = ' ';
wid = 1;
repeat:
fmt++; /* Skip '%' initially, other stuff later */
switch(*fmt) {
case '\0':
goto ret;
case '0':
lead = '0';
goto repeat;
case '*':
/* should be precision, just eat it */
base = va_arg(args, int);
/* fall through: discard unknown stuff */
default:
if (*fmt >= '1' && *fmt <= '9')
wid = *fmt - '0';
goto repeat;
/* Special cases for conversions */
case 'c': /* char: supported */
*str++ = (unsigned char) va_arg(args, int);
break;
case 's': /* string: supported */
s = va_arg(args, char *);
while (*s)
*str++ = *s++;
break;
case 'n': /* number-thus-far: not supported */
break;
case '%': /* supported */
*str++ = '%';
break;
/* integers are more or less printed */
case 'p':
case 'x':
case 'X':
base = 16;
case 'o':
if (base == 10) /* yet unchaged */
base = 8;
case 'd':
case 'i':
case 'u':
str += number(str, va_arg(args, int), base, lead, wid);
break;
}
}
ret:
*str = '\0';
return str - buf;
}
sw/mcu/Makefile 0 → 100644
View file @ 6896864b
-include Makefile.specific
CROSS_COMPILE ?= riscv32-elf-
CPU = urv
OBJS = main.o
OUTPUT = test
include ../arch/urv/urv.mk
sw/mcu/main.c 0 → 100644
View file @ 6896864b
#include <stdio.h>
#include "uart.h"
#include "pp-printf.h"
int main()
{
uart_init_hw();
pp_printf("Hello!\n");
for(;;)
return 0;
}
\ No newline at end of file
syn/spec_test/Manifest.py 0 → 100644
View file @ 6896864b
target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
syn_tool = "ise"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_tdc_test.xise"
modules = { "local" : [ "../../top/spec_test" ] }
#files = "wrc-release.ram"
\ No newline at end of file
syn/spec_test/spec_tdc_test.xise 0 → 100644
View file @ 6896864b
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../rtl/tdc_order_picker.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../top/spec_test/spec_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../rtl/tdc_ringosc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../rtl/tdc_ordertaps.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../rtl/xwb_urv_mcs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../rtl/tdc_channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../rtl/tdc_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../ip_cores/urv-core/rtl/xurv_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../rtl/tdc_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../top/spec_test/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
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<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_top_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_top_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_top_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_top_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="spec_tdc_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-09-12T16:24:17" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BE457104762C7276B72B97A1EFAED0A3" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/spec_top" xil_pn:name="../../top/spec_test/spec_top.ucf"/>
</bindings>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="../../ip_cores/urv-core/rtl/urv_defs.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/urv-core/rtl/urv_config.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
</project>
top/spec_test/Manifest.py 0 → 100644
View file @ 6896864b
files = ["spec_top.ucf",
"spec_top.vhd",
"spec_reset_gen.vhd"];
fetchto = "../../ip_cores"
modules = {
"local" : [ "../../rtl/", "../../ip_cores/gn4124-core" ]
}
top/spec_test/spec_reset_gen.vhd 0 → 100644
View file @ 6896864b
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
top/spec_test/spec_top.ucf 0 → 100644
View file @ 6896864b
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
#####################################################################
### Gennum ports
#####################################################################
NET "gn_rst_n" LOC = N20;
NET "gn_rst_n" IOSTANDARD = "LVCMOS18";
NET "gn_gpio[1]" LOC = U16;
NET "gn_gpio[1]" IOSTANDARD = "LVCMOS25";
NET "gn_gpio[0]" LOC = AB19;
NET "gn_gpio[0]" IOSTANDARD = "LVCMOS25";
NET "gn_p2l_rdy" LOC = J16;
NET "gn_p2l_rdy" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_clkn" LOC = M19;
NET "gn_p2l_clkn" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_clkp" LOC = M20;
NET "gn_p2l_clkp" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_data[0]" LOC = K20;
NET "gn_p2l_data[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[1]" LOC = H22;
NET "gn_p2l_data[1]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[2]" LOC = H21;
NET "gn_p2l_data[2]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[3]" LOC = L17;
NET "gn_p2l_data[3]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[4]" LOC = K17;
NET "gn_p2l_data[4]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[5]" LOC = G22;
NET "gn_p2l_data[5]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[6]" LOC = G20;
NET "gn_p2l_data[6]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[7]" LOC = K18;
NET "gn_p2l_data[7]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[8]" LOC = K19;
NET "gn_p2l_data[8]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[9]" LOC = H20;
NET "gn_p2l_data[9]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[10]" LOC = J19;
NET "gn_p2l_data[10]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[11]" LOC = E22;
NET "gn_p2l_data[11]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[12]" LOC = E20;
NET "gn_p2l_data[12]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[13]" LOC = F22;
NET "gn_p2l_data[13]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[14]" LOC = F21;
NET "gn_p2l_data[14]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data[15]" LOC = H19;
NET "gn_p2l_data[15]" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_dframe" LOC = J22;
NET "gn_p2l_dframe" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_valid" LOC = L19;
NET "gn_p2l_valid" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req[0]" LOC = M22;
NET "gn_p_wr_req[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req[1]" LOC = M21;
NET "gn_p_wr_req[1]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy[0]" LOC = L15;
NET "gn_p_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy[1]" LOC = K16;
NET "gn_p_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
NET "gn_rx_error" LOC = J17;
NET "gn_rx_error" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[0]" LOC = P16;
NET "gn_l2p_data[0]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[1]" LOC = P21;
NET "gn_l2p_data[1]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[2]" LOC = P18;
NET "gn_l2p_data[2]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[3]" LOC = T20;
NET "gn_l2p_data[3]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[4]" LOC = V21;
NET "gn_l2p_data[4]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[5]" LOC = V19;
NET "gn_l2p_data[5]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[6]" LOC = W22;
NET "gn_l2p_data[6]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[7]" LOC = Y22;
NET "gn_l2p_data[7]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[8]" LOC = P22;
NET "gn_l2p_data[8]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[9]" LOC = R22;
NET "gn_l2p_data[9]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[10]" LOC = T21;
NET "gn_l2p_data[10]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[11]" LOC = T19;
NET "gn_l2p_data[11]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[12]" LOC = V22;
NET "gn_l2p_data[12]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[13]" LOC = V20;
NET "gn_l2p_data[13]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[14]" LOC = W20;
NET "gn_l2p_data[14]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data[15]" LOC = Y21;
NET "gn_l2p_data[15]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_dframe" LOC = U22;
NET "gn_l2p_dframe" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_valid" LOC = T18;
NET "gn_l2p_valid" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_clkn" LOC = K22;
NET "gn_l2p_clkn" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_clkp" LOC = K21;
NET "gn_l2p_clkp" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_edb" LOC = U20;
NET "gn_l2p_edb" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_rdy" LOC = U19;
NET "gn_l2p_rdy" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy[0]" LOC = R20;
NET "gn_l_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy[1]" LOC = T22;
NET "gn_l_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy[0]" LOC = N16;
NET "gn_p_rd_d_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy[1]" LOC = P19;
NET "gn_p_rd_d_rdy[1]" IOSTANDARD = "SSTL18_I";
NET "gn_tx_error" LOC = M17;
NET "gn_tx_error" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy[0]" LOC = B21;
NET "gn_vc_rdy[0]" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy[1]" LOC = B22;
NET "gn_vc_rdy[1]" IOSTANDARD = "SSTL18_I";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
#----------------------------------------
# False Path
#----------------------------------------
# GN4124
NET "gn_rst_n" TIG;
#NET "gen_with_gennum/cmp_gn4124_core/rst_*" TIG;
#NET "gen_with_gennum/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
NET "clk_sys_62m5" TNM_NET = clk_sys_62m5;
NET "gn_rst_n" TIG;
NET "gen_with_gennum.cmp_gn4124_core/rst_reg_d" TIG;
NET "*/tdc_inv_input_signal" TIG;
NET "clk_125m_pllref_p_i" CLOCK_DEDICATED_ROUTE = FALSE;
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
NET "/clk_ref" TNM_NET = "clk_ref";
NET "/clk_cal" TNM_NET = "clk_cal";
TIMESPEC TS_crossdomain_1 = FROM "clk_ref" TO "clk_cal" 10ns DATAPATHONLY;
TIMESPEC TS_crossdomain_2 = FROM "clk_cal" TO "clk_ref" 10ns DATAPATHONLY;
#TIMEGRP "synchronizers"="sync_ffs" "sync_reg";
#TIMEGRP "ref_sync"="synchronizers" EXCEPT "clk_ref";
#TIMEGRP "sys_sync"="synchronizers" EXCEPT "clk_sys_62m5";
#TIMEGRP "cal_sync"="synchronizers" EXCEPT "clk_cal";
#TIMESPEC TS_ref_sync_ffs = FROM "cal_sync" TO "ref_sync" 10ns DATAPATHONLY;
top/spec_test/spec_top.vhd 0 → 100644
View file @ 6896864b
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity spec_top is
generic
(g_simulation : boolean := false;
g_sim_bypass_gennum : boolean := false
);
-- when instantiated in a test-bench
port(
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
------------------------------------------------------------------------
-- GN4124 PCI bridge pins
------------------------------------------------------------------------
gn_rst_n : in std_logic; -- reset from gn4124 (rstout18_n)
-- general purpose interface
gn_gpio : out std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
-- pcie to local [inbound data] - rx
gn_p2l_rdy : out std_logic; -- rx buffer full flag
gn_p2l_clkn : in std_logic; -- receiver source synchronous clock-
gn_p2l_clkp : in std_logic; -- receiver source synchronous clock+
gn_p2l_data : in std_logic_vector(15 downto 0); -- parallel receive data
gn_p2l_dframe : in std_logic; -- receive frame
gn_p2l_valid : in std_logic; -- receive data valid
-- inbound buffer request/status
gn_p_wr_req : in std_logic_vector(1 downto 0); -- pcie write request
gn_p_wr_rdy : out std_logic_vector(1 downto 0); -- pcie write ready
gn_rx_error : out std_logic; -- receive error
-- local to parallel [outbound data] - tx
gn_l2p_data : out std_logic_vector(15 downto 0); -- parallel transmit data
gn_l2p_dframe : out std_logic; -- transmit data frame
gn_l2p_valid : out std_logic; -- transmit data valid
gn_l2p_clkn : out std_logic; -- transmitter source synchronous clock-
gn_l2p_clkp : out std_logic; -- transmitter source synchronous clock+
gn_l2p_edb : out std_logic; -- packet termination and discard
-- outbound buffer status
gn_l2p_rdy : in std_logic; -- tx buffer full flag
gn_l_wr_rdy : in std_logic_vector(1 downto 0); -- local-to-pcie write
gn_p_rd_d_rdy : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
gn_tx_error : in std_logic; -- transmit error
gn_vc_rdy : in std_logic_vector(1 downto 0) -- channel ready
-- Bypass GN4124 core, useful only in simulation
-- Feed fake timestamps bypassing acam - used only in simulation
-- synthesis translate_off
;
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
sim_wb_o : out t_wishbone_slave_out
-- synthesis translate_on
);
end spec_top;
architecture rtl of spec_top is
function f_bool2int (x : boolean) return integer is
begin
if(x) then
return 1;
else
return 0;
end if;
end f_bool2int;
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
constant c_WB_SLAVE_TDC : integer := 0;
-- Slave port on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
constant c_MASTER_GENNUM : integer := 0;
constant c_CNX_BASE_ADDR : t_wishbone_address_array(0 to 0) :=
(c_WB_SLAVE_TDC => x"00000000");
constant c_CNX_BASE_MASK : t_wishbone_address_array(0 to 0) :=
(c_WB_SLAVE_TDC => x"000F0000");
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- Clocks and resets
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal gn_wb_adr : std_logic_vector(31 downto 0);
function f_to_string(x : boolean) return string is
begin
if x then
return "TRUE";
else
return "FALSE";
end if;
end f_to_string;
signal pll_arst : std_logic := '0';
signal clk_125m_pllref_buf : std_logic;
signal clk_sys_prebuf, clk_sys_fb : std_logic;
signal clk_ref_prebuf, clk_ref : std_logic;
signal clk_cal1_fb, clk_cal2_fb, clk_cal1, clk_cal2, clk_cal1_prebuf, clk_cal2_prebuf : std_logic;
signal pll_sys_locked : std_logic;
signal gn4124_status : std_logic_vector(31 downto 0);
signal rst_ref_n : std_logic;
signal clk_cal : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
U_Reset_Gen: entity work.spec_reset_gen
port map (
clk_sys_i => clk_sys_62m5,
rst_pcie_n_a_i => gn_rst_n,
rst_button_n_a_i => '1',
rst_n_o => rst_sys_62m5_n);
-- active high async reset for PLLs
pll_arst <= not gn_rst_n;
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => clk_sys_fb,
CLKOUT0 => clk_sys_prebuf,
CLKOUT1 => clk_ref_prebuf,
LOCKED => pll_sys_locked,
RST => pll_arst,
CLKFBIN => clk_sys_fb,
CLKIN => clk_125m_pllref_buf);
-- System PLL input clock buffer
cmp_clk_sys_buf_i : IBUFGDS
port map (
O => clk_125m_pllref_buf,
I => clk_125m_pllref_p_i,
IB => clk_125m_pllref_n_i);
-- System PLL output clock buffer
cmp_clk_sys_buf_o : BUFG
port map (
O => clk_sys_62m5,
I => clk_sys_prebuf);
-- System PLL output clock buffer
cmp_clk_ref_buf_o : BUFG
port map (
O => clk_ref,
I => clk_ref_prebuf);
cmp_cal_clk_pll_1 : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 4,
CLKFBOUT_MULT => 31,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 32,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => clk_cal1_fb,
CLKOUT0 => clk_cal1_prebuf,
RST => pll_arst,
CLKFBIN => clk_cal1_fb,
CLKIN => clk_125m_pllref_buf);
cmp_clk_cal1_buf : BUFG
port map (
O => clk_cal1,
I => clk_cal1_prebuf);
cmp_cal_clk_pll_2 : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 33,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 33.03,
REF_JITTER => 0.016)
port map (
CLKFBOUT => clk_cal2_fb,
CLKOUT0 => clk_cal2_prebuf,
RST => pll_arst,
CLKFBIN => clk_cal2_fb,
CLKIN => clk_cal1);
-- System PLL output clock buffer
cmp_clk_cal2_buf : BUFG
port map (
O => clk_cal,
I => clk_cal2_prebuf);
cmp_sdb_crossbar : xwb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_address => c_CNX_BASE_ADDR,
g_mask => c_CNX_BASE_MASK)
port map
(clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
---------------------------------------------------------------------------------------------------
-- GN4124 CORE --
---------------------------------------------------------------------------------------------------
gen_with_gennum : if g_sim_bypass_gennum = false generate
cmp_gn4124_core : gn4124_core
port map
(rst_n_a_i => gn_rst_n,
status_o => gn4124_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => gn_p2l_clkp,
p2l_clk_n_i => gn_p2l_clkn,
p2l_data_i => gn_p2l_data,
p2l_dframe_i => gn_p2l_dframe,
p2l_valid_i => gn_p2l_valid,
-- P2L Control
p2l_rdy_o => gn_p2l_rdy,
p_wr_req_i => gn_p_wr_req,
p_wr_rdy_o => gn_p_wr_rdy,
rx_error_o => gn_rx_error,
vc_rdy_i => gn_vc_rdy,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => gn_l2p_clkp,
l2p_clk_n_o => gn_l2p_clkn,
l2p_data_o => gn_l2p_data,
l2p_dframe_o => gn_l2p_dframe,
l2p_valid_o => gn_l2p_valid,
-- L2P Control
l2p_edb_o => gn_l2p_edb,
l2p_rdy_i => gn_l2p_rdy,
l_wr_rdy_i => gn_l_wr_rdy,
p_rd_d_rdy_i => gn_p_rd_d_rdy,
tx_error_i => gn_tx_error,
irq_p_i => '0',
irq_p_o => open,
-- CSR WISHBONE interface (master pipelined)
csr_clk_i => clk_sys_62m5,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
csr_err_i => '0',
csr_rty_i => '0'
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Convert 32-bit word address into byte address for crossbar
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
gn_gpio <= (others => '0');
end generate gen_with_gennum;
gen_without_gennum : if g_sim_bypass_gennum generate
-- synthesis translate_off
cnx_slave_in(c_MASTER_GENNUM) <= sim_wb_i;
sim_wb_o <= cnx_slave_out(c_MASTER_GENNUM);
-- synthesis translate_on
end generate gen_without_gennum;
U_Sync_Ref_Reset : gc_sync_ffs
port map (
clk_i => clk_ref,
rst_n_i => '1',
data_i => rst_sys_62m5_n,
synced_o => rst_ref_n);
U_TDC_Core: entity work.tdc_core
port map (
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
clk_tdc_i => clk_ref,
rst_tdc_n_i => rst_ref_n,
clk_cal_i => clk_cal,
signal_i => '0',
slave_i => cnx_master_out(c_WB_SLAVE_TDC),
slave_o => cnx_master_in(c_WB_SLAVE_TDC),
dbg_txd_o => uart_txd_o,
dbg_rxd_i => uart_rxd_i);
end rtl;
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