... | @@ -43,6 +43,7 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -43,6 +43,7 @@ core for Xilinx Spartan-6 FPGAs. |
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- Reset.
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- Reset.
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- Clock.
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- Clock.
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- Output signals (without host interface module):
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- Output signals (without host interface module):
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- Startup calibration in progress.
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- Periodic counter overflow.
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- Periodic counter overflow.
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- Received rising/falling edge notification:
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- Received rising/falling edge notification:
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- Strobe signal.
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- Strobe signal.
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... | @@ -51,7 +52,7 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -51,7 +52,7 @@ core for Xilinx Spartan-6 FPGAs. |
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- Raw encoded value from the delay line.
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- Raw encoded value from the delay line.
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- Debug interface:
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- Debug interface:
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- Forced switch to the calibration signal.
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- Forced switch to the calibration signal.
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- Access to the histogram values.
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- Access to the histogram values from the startup calibration.
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- Optional host/CPU interface module:
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- Optional host/CPU interface module:
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- Wishbone slave.
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- Wishbone slave.
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- Configuration and status registers.
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- Configuration and status registers.
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