... | ... | @@ -13,7 +13,7 @@ core for Xilinx Spartan-6 FPGAs. |
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- With a 125MHz FPGA clock, LSB corresponds to 0.98ps.
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- Typical range: 268ms (using a \<25.13\>-bit value at 125MHz).
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- Number of coarse counter bits configurable with a VHDL generic.
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- Latency: 5 cycles at 125MHz (not including host interface module).
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- Latency: 6 cycles at 125MHz (not including host interface module).
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- Multiple channels.
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- Configurable with a VHDL generic.
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- Calibration logic shared between channels.
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