... | @@ -10,10 +10,10 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -10,10 +10,10 @@ core for Xilinx Spartan-6 FPGAs. |
|
- Fixed point output:
|
|
- Fixed point output:
|
|
- Integer part is number of FPGA clocks (coarse counter).
|
|
- Integer part is number of FPGA clocks (coarse counter).
|
|
- 13-bit fractional part.
|
|
- 13-bit fractional part.
|
|
- With a 10ns FPGA clock, LSB corresponds to 1.22ps.
|
|
- With a 8ns FPGA clock, LSB corresponds to 0.98ps.
|
|
- Typical range: 340ms (using a \<25.13\>-bit value).
|
|
- Typical range: 340ms (using a \<25.13\>-bit value).
|
|
- Number of coarse counter bits configurable with a VHDL generic.
|
|
- Number of coarse counter bits configurable with a VHDL generic.
|
|
- Latency: 4 to 6 cycles (not including host interface module).
|
|
- Latency: 5 cycles at 125MHz (not including host interface module).
|
|
- Multiple channels.
|
|
- Multiple channels.
|
|
- Configurable with a VHDL generic.
|
|
- Configurable with a VHDL generic.
|
|
- Calibration logic shared between channels.
|
|
- Calibration logic shared between channels.
|
... | | ... | |