... | ... | @@ -9,6 +9,8 @@ core for Xilinx Spartan-6 FPGAs. |
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- Expected precision: 50-100ps.
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- Typical range: 200ms (using a 32-bit value and 50ps steps).
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- Latency: 4 to 6 cycles (not including host interface module).
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- One channel (but the core can be implemented several times in the
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same FPGA for multiple channels).
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- Uses a counter for coarse timing and a calibrated delay line for
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fine timing.
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- Range: number of counter bits configurable with a VHDL generic.
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