... | @@ -6,16 +6,19 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -6,16 +6,19 @@ core for Xilinx Spartan-6 FPGAs. |
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# Specifications
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# Specifications
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- Range?
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- Expected precision: 50-100ps.
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- Typical range: 200ms (using a 32-bit value and 50ps steps).
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- Latency: 4 to 6 cycles (not including host interface module).
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- Uses a counter for coarse timing and a calibrated delay line for
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- Uses a counter for coarse timing and a calibrated delay line for
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fine timing.
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fine timing.
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- Range: number of output bits configurable with a VHDL generic.
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- Delay line implemented with carry chain (CARRY4) primitives.
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- Delay line implemented with carry chain (CARRY4) primitives.
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- Histogram booking an calibration as explained in the [Fermilab
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- Histogram booking and calibration as explained in the [Fermilab
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paper](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf)
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paper](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf).
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- Wishbone slave interface (with configuration and status registers)
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- Host interface module:
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to read back the data.
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- Wishbone slave.
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- Expected precision: 50-100ps.
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- Configuration and status registers.
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- Typical range: .
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- Interrupts: pulse received, counter overflow.
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# Deliverables
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# Deliverables
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... | @@ -23,10 +26,13 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -23,10 +26,13 @@ core for Xilinx Spartan-6 FPGAs. |
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- VHDL testbench for the core.
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- VHDL testbench for the core.
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- Report with real measurements using the SPEC and digital I/O FMC
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- Report with real measurements using the SPEC and digital I/O FMC
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boards.
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boards.
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- Documentation for users of the
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- Documentation for users of the core.
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core.
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- Demonstration design for the SPEC board.
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h1. Envisioned
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applications
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# Applications
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<!-- end list -->
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- [fmc-delay-1ns-8cha](https://www.ohwr.org/project/fmc-delay-1ns-8cha)
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- [fmc-delay-1ns-8cha](https://www.ohwr.org/project/fmc-delay-1ns-8cha)
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- [fmc-tdc](https://www.ohwr.org/project/fmc-tdc)
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