... | ... | @@ -40,6 +40,7 @@ core for Xilinx Spartan-6 FPGAs. |
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- Input signal.
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- Calibration signal.
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- Coarse counter reset.
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- Per-channel de-skew value.
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- Full reset (and recalibrate).
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- Clock.
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- Output signals (without host interface module):
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... | ... | @@ -53,6 +54,8 @@ core for Xilinx Spartan-6 FPGAs. |
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- Debug interface:
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- Forced switch to the calibration signal.
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- Access to the histogram values from the startup calibration.
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- Access to the frequency of the online calibration ring
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oscillator.
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- Optional host/CPU interface module:
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- Wishbone slave.
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- Configuration and status registers.
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