... | ... | @@ -24,10 +24,10 @@ core for Xilinx Spartan-6 FPGAs. |
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fine timing.
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- Delay line implemented with carry chain (CARRY4) primitives.
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- Calibration mechanism:
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- at startup (and after receiving a recalibrate command), send
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random pulses into the delay line (coming from e.g. a on-chip
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ring oscillator), build histogram, compute delays (as explained
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in the [Fermilab
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- at startup (and after receiving a reset command), send random
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pulses into the delay line (coming from e.g. a on-chip ring
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oscillator), build histogram, compute delays (as explained in
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the [Fermilab
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paper](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf)),
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initialize the LUT, and measure the frequency of the
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compensation ring oscillator.
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... | ... | @@ -37,15 +37,25 @@ core for Xilinx Spartan-6 FPGAs. |
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update the LUT.
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- "Wave union" not implemented.
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- Input signals (without host interface module):
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- Coarse counter reset.
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- Input signal.
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- Calibration signal.
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- Coarse counter reset.
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- Reset.
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- Clock.
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- Output signals (without host interface module):
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- Periodic counter overflow.
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- Received pulse notification (with counter value + fine timing).
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- Received rising/falling edge notification:
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- Strobe signal.
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- Rising/falling edge.
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- Fixed point timestamp.
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- Raw encoded value from the delay line.
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- Debug interface:
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- Forced switch to the calibration signal.
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- Access to the histogram values.
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- Optional host/CPU interface module:
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- Wishbone slave.
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- Configuration and status registers.
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- Level-sensitive interrupts: pulse received, counter overflow.
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- Level-sensitive interrupts: edge received, counter overflow.
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# Deliverables
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... | ... | |