... | @@ -17,6 +17,9 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -17,6 +17,9 @@ core for Xilinx Spartan-6 FPGAs. |
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- Multiple channels.
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- Multiple channels.
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- Configurable with a VHDL generic.
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- Configurable with a VHDL generic.
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- Calibration logic shared between channels.
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- Calibration logic shared between channels.
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- Reports both rising and falling edges of the input signal.
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- Input signal must not have transitions shorter than the FPGA clock
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period.
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- Uses a counter for coarse timing and a calibrated delay line for
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- Uses a counter for coarse timing and a calibrated delay line for
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fine timing.
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fine timing.
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- Delay line implemented with carry chain (CARRY4) primitives.
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- Delay line implemented with carry chain (CARRY4) primitives.
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... | @@ -33,6 +36,9 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -33,6 +36,9 @@ core for Xilinx Spartan-6 FPGAs. |
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measured at start-up, linearly interpolate the delays, and
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measured at start-up, linearly interpolate the delays, and
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update the LUT.
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update the LUT.
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- "Wave union" not implemented.
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- "Wave union" not implemented.
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- Input signals (without host interface module):
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- Coarse counter reset.
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- Calibration signal.
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- Output signals (without host interface module):
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- Output signals (without host interface module):
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- Periodic counter overflow.
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- Periodic counter overflow.
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- Received pulse notification (with counter value + fine timing).
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- Received pulse notification (with counter value + fine timing).
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