... | ... | @@ -59,7 +59,7 @@ core for Xilinx Spartan-6 FPGAs. |
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- Optional host/CPU interface module:
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- Wishbone slave.
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- Configuration and status registers.
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- Level-sensitive interrupts: edge received, counter overflow.
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- Interrupts: edge received, counter overflow.
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# Deliverables
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