... | ... | @@ -75,3 +75,30 @@ core for Xilinx Spartan-6 FPGAs. |
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- [fmc-delay-1ns-8cha](https://www.ohwr.org/project/fmc-delay-1ns-8cha)
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- [fmc-tdc](https://www.ohwr.org/project/fmc-tdc)
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# Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><strong>Event</strong></td>
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</tr>
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<tr class="even">
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<td>18/07/2011</td>
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<td>Project started</td>
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</tr>
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<tr class="odd">
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<td>28/07/2011</td>
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<td>Specification written</td>
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</tr>
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<tr class="even">
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<td>01/08/2011</td>
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<td>Development started</td>
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</tr>
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<tr class="odd">
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<td>05/08/2011</td>
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<td>Basic data path of the TDC (delay line + encoder + LUT) designed. Timing is met at 125MHz with a 400-tap ~12ns delay line. Total latency is 5 cycles (40ns).</td>
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</tr>
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</tbody>
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</table>
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