... | @@ -15,23 +15,25 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -15,23 +15,25 @@ core for Xilinx Spartan-6 FPGAs. |
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- Delay line implemented with carry chain (CARRY4) primitives.
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- Delay line implemented with carry chain (CARRY4) primitives.
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- Histogram booking and calibration as explained in the [Fermilab
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- Histogram booking and calibration as explained in the [Fermilab
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paper](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf).
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paper](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf).
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- Host interface module:
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- Output signals: counter overflow
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- Optional host interface module:
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- Wishbone slave.
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- Wishbone slave.
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- Configuration and status registers.
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- Configuration and status registers.
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- Interrupts: pulse received, counter overflow.
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- Interrupts: pulse received, counter overflow.
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# Deliverables
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# Deliverables
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- VHDL core using the CERN coding guidelines.
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- VHDL core using the [CERN coding
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guidelines](https://www.ohwr.org/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines).
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- VHDL testbench for the core.
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- VHDL testbench for the core.
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- Report with real measurements using the SPEC and digital I/O FMC
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- Report with real measurements using
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boards.
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[spec](https://www.ohwr.org/project/spec) and
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[fmc-dio-5chttla.](https://www.ohwr.org/project/fmc-dio-5chttla).
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- Documentation for users of the core.
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- Documentation for users of the core.
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- Demonstration design for the SPEC board.
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- Demonstration design for the SPEC
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h1. Envisioned
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board.
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applications
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<!-- end list -->
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# Envisioned applications
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- [fmc-delay-1ns-8cha](https://www.ohwr.org/project/fmc-delay-1ns-8cha)
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- [fmc-delay-1ns-8cha](https://www.ohwr.org/project/fmc-delay-1ns-8cha)
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- [fmc-tdc](https://www.ohwr.org/project/fmc-tdc)
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- [fmc-tdc](https://www.ohwr.org/project/fmc-tdc)
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