... | @@ -18,8 +18,8 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -18,8 +18,8 @@ core for Xilinx Spartan-6 FPGAs. |
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- Configurable with a VHDL generic.
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- Configurable with a VHDL generic.
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- Calibration logic shared between channels.
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- Calibration logic shared between channels.
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- Reports both rising and falling edges of the input signal.
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- Reports both rising and falling edges of the input signal.
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- Input signal must not have transitions shorter than the FPGA clock
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- Input signal must not have transitions shorter than three times the
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period.
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FPGA clock period.
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- Uses a counter for coarse timing and a calibrated delay line for
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- Uses a counter for coarse timing and a calibrated delay line for
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fine timing.
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fine timing.
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- Delay line implemented with carry chain (CARRY4) primitives.
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- Delay line implemented with carry chain (CARRY4) primitives.
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