... | @@ -96,6 +96,10 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -96,6 +96,10 @@ core for Xilinx Spartan-6 FPGAs. |
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<td>05/08/2011</td>
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<td>05/08/2011</td>
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<td>Basic data path of the TDC (delay line + encoder + LUT) designed. Timing is met at 125MHz with a 400-tap ~12ns delay line. Total latency is 5 cycles (40ns).</td>
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<td>Basic data path of the TDC (delay line + encoder + LUT) designed. Timing is met at 125MHz with a 400-tap ~12ns delay line. Total latency is 5 cycles (40ns).</td>
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</tr>
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</tr>
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<tr class="even">
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<td>21/08/2011</td>
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<td>"Alpha" design done. Still needs more test benches and documentation.</td>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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