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# Project description
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# Project description
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The TDC core is a high precision (sub-nanosecond) [time to digital conversion](http://en.wikipedia.org/wikis/Time_to_digital_converter) core for Xilinx Spartan-6 FPGAs.
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The TDC core is a high precision (sub-nanosecond) [time to digital
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conversion](http://en.wikipedia.org/wikis/Time_to_digital_converter)
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core for Xilinx Spartan-6 FPGAs.
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# Specifications
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# Specifications
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- Based on a calibrated delay line
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- Range?
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- Delay line implemented with carry chain (CARRY4) primitives
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- Uses a counter for coarse timing and a calibrated delay line for
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- Expected precision: 50-100ps
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fine timing.
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- Delay line implemented with carry chain (CARRY4) primitives.
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- Histogram booking an calibration as explained in the [Fermilab
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paper](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf)
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- Wishbone slave interface (with configuration and status registers)
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to read back the data.
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- Expected precision: 50-100ps.
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- Typical range: .
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# Deliverables
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- VHDL core using the CERN coding guidelines.
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- VHDL testbench for the core.
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- Report with real measurements using the SPEC and digital I/O FMC
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boards.
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- Documentation for users of the
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core.
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# Applications
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- [fmc-delay-1ns-8cha](https://www.ohwr.org/project/fmc-delay-1ns-8cha)
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