... | @@ -15,11 +15,13 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -15,11 +15,13 @@ core for Xilinx Spartan-6 FPGAs. |
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- Delay line implemented with carry chain (CARRY4) primitives.
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- Delay line implemented with carry chain (CARRY4) primitives.
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- Histogram booking and calibration as explained in the [Fermilab
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- Histogram booking and calibration as explained in the [Fermilab
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paper](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf).
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paper](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf).
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- Output signals: counter overflow
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- Output signals (without host interface module):
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- Optional host interface module:
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- Periodic counter overflow
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- Received pulse notification (with counter value + fine timing)
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- Optional host/CPU interface module:
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- Wishbone slave.
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- Wishbone slave.
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- Configuration and status registers.
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- Configuration and status registers.
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- Interrupts: pulse received, counter overflow.
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- Level-sensitive interrupts: pulse received, counter overflow.
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# Deliverables
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# Deliverables
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