... | @@ -75,50 +75,18 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -75,50 +75,18 @@ core for Xilinx Spartan-6 FPGAs. |
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# Status
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# Status
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<table>
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|Date|Event|
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<tbody>
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|----|----|
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<tr class="odd">
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|18/07/2011|Project started.|
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<td><strong>Date</strong></td>
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|28/07/2011|Specification written.|
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<td><strong>Event</strong></td>
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|01/08/2011|Development started.|
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</tr>
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|05/08/2011|Basic data path of the TDC (delay line + encoder + LUT) designed. Timing is met at 125MHz with a 400-tap ~12ns delay line. Total latency is 5 cycles (40ns).|
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<tr class="even">
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|21/08/2011|"Alpha" design done. Still needs more test benches and documentation.|
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<td>18/07/2011</td>
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|26/08/2011|Host interface module done.|
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<td>Project started.</td>
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|28/08/2011|"Beta" design done. [PDF documentation](https://www.ohwr.org/project/tdc-core/wikis/Documents/User-guide) is in the "Documents" section.|
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</tr>
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|21/10/2011|Hardware tests started.|
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<tr class="odd">
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|09/11/2011|[Test results](https://www.ohwr.org/project/tdc-core/wikis/Documents/Test-report) available.|
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<td>28/07/2011</td>
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<td>Specification written.</td>
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</tr>
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<tr class="even">
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<td>01/08/2011</td>
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<td>Development started.</td>
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</tr>
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<tr class="odd">
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<td>05/08/2011</td>
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<td>Basic data path of the TDC (delay line + encoder + LUT) designed. Timing is met at 125MHz with a 400-tap ~12ns delay line. Total latency is 5 cycles (40ns).</td>
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</tr>
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<tr class="even">
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<td>21/08/2011</td>
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<td>"Alpha" design done. Still needs more test benches and documentation.</td>
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</tr>
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<tr class="odd">
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<td>26/08/2011</td>
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<td>Host interface module done.</td>
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</tr>
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<tr class="even">
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<td>28/08/2011</td>
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<td>"Beta" design done. <a href="https://www.ohwr.org/project/tdc-core/wikis/Documents/User-guide">PDF documentation</a> is in the "Documents" section.</td>
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</tr>
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<tr class="odd">
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<td>21/10/2011</td>
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<td>Hardware tests started.</td>
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</tr>
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<tr class="even">
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<td>09/11/2011</td>
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<td><a href="https://www.ohwr.org/project/tdc-core/wikis/Documents/Test-report">Test results</a> available.</td>
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</tr>
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</tbody>
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</table>
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# Envisioned applications
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# Envisioned applications
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... | @@ -134,3 +102,4 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -134,3 +102,4 @@ core for Xilinx Spartan-6 FPGAs. |
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FPGA TDC Resolution beyond Its Cell Delay*
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FPGA TDC Resolution beyond Its Cell Delay*
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[PDF](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf)
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[PDF](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf)
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