... | ... | @@ -54,8 +54,8 @@ core for Xilinx Spartan-6 FPGAs. |
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- Debug interface:
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- Forced switch to the calibration signal.
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- Access to the histogram values from the startup calibration.
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- Access to the frequency of the online calibration ring
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oscillator.
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- Access to the frequencies of the online calibration ring
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oscillators.
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- Optional host/CPU interface module:
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- Wishbone slave.
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- Configuration and status registers.
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