... | ... | @@ -6,17 +6,32 @@ core for Xilinx Spartan-6 FPGAs. |
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# Specifications
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- Expected precision: 50-100ps.
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- Typical range: 200ms (using a 32-bit value and 50ps steps).
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- Expected precision: 50-100ps (peak to peak).
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- Fixed point output:
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- Integer part is number of FPGA clocks (coarse counter).
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- 13-bit fractional part.
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- With a 10ns FPGA clock, LSB corresponds to 1.22ps.
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- Typical range: 340ms (using a \<25.13\>-bit value).
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- Number of coarse counter bits configurable with a VHDL generic.
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- Latency: 4 to 6 cycles (not including host interface module).
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- One channel (but the core can be implemented several times in the
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same FPGA for multiple channels).
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- Multiple channels.
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- Configurable with a VHDL generic.
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- Calibration logic shared between channels.
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- Uses a counter for coarse timing and a calibrated delay line for
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fine timing.
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- Range: number of counter bits configurable with a VHDL generic.
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- Delay line implemented with carry chain (CARRY4) primitives.
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- Histogram booking and calibration as explained in the [Fermilab
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paper](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf).
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- Calibration mechanism:
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- at startup (and after receiving a recalibrate command), send
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random pulses into the delay line (coming from e.g. a on-chip
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ring oscillator), build histogram, compute delays (as explained
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in the [Fermilab
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paper](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf)),
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initialize the LUT, and measure the frequency of the
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compensation ring oscillator.
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- for online temperature/voltage compensation, measure again the
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frequency of the ring oscillator, compare it to the frequency
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measured at start-up, linearly interpolate the delays, and
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update the LUT.
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- "Wave union" not implemented.
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- Output signals (without host interface module):
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- Periodic counter overflow.
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