... | ... | @@ -11,7 +11,7 @@ core for Xilinx Spartan-6 FPGAs. |
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- Latency: 4 to 6 cycles (not including host interface module).
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- Uses a counter for coarse timing and a calibrated delay line for
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fine timing.
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- Range: number of output bits configurable with a VHDL generic.
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- Range: number of counter bits configurable with a VHDL generic.
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- Delay line implemented with carry chain (CARRY4) primitives.
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- Histogram booking and calibration as explained in the [Fermilab
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paper](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf).
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