... | ... | @@ -15,6 +15,7 @@ core for Xilinx Spartan-6 FPGAs. |
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- Delay line implemented with carry chain (CARRY4) primitives.
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- Histogram booking and calibration as explained in the [Fermilab
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paper](http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/PID765918.pdf).
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- "Wave union" not implemented.
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- Output signals (without host interface module):
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- Periodic counter overflow.
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- Received pulse notification (with counter value + fine timing).
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