... | @@ -66,8 +66,8 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -66,8 +66,8 @@ core for Xilinx Spartan-6 FPGAs. |
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- VHDL core using the [CERN coding
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- VHDL core using the [CERN coding
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guidelines](https://www.ohwr.org/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines).
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guidelines](https://www.ohwr.org/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines).
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- VHDL testbench for the core.
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- VHDL testbench for the core.
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- Report with real measurements using
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- [Report with real measurements](https://www.ohwr.org/project/tdc-core/wikis/Documents/Test-report)
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[spec](https://www.ohwr.org/project/spec) and
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using [spec](https://www.ohwr.org/project/spec) and
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[fmc-dio-5chttla.](https://www.ohwr.org/project/fmc-dio-5chttla).
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[fmc-dio-5chttla.](https://www.ohwr.org/project/fmc-dio-5chttla).
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- Documentation for users of the core.
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- Documentation for users of the core.
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- Demonstration design for the SPEC board.
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- Demonstration design for the SPEC board.
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... | @@ -114,7 +114,7 @@ core for Xilinx Spartan-6 FPGAs. |
... | @@ -114,7 +114,7 @@ core for Xilinx Spartan-6 FPGAs. |
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>09/11/2011</td>
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<td>09/11/2011</td>
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<td>Test results available.</td>
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<td><a href="https://www.ohwr.org/project/tdc-core/wikis/Documents/Test-report">Test results</a> available.</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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... | | ... | |