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Simple VME FMC Carrier 7 - SVEC7
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Simple VME FMC Carrier 7 - SVEC7
Issues
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sfpga: read dtack
#34
· opened
Apr 07, 2020
by
Tristan Gingold
Ready for PCB layout review.
design
CLOSED
1
4
updated
Jul 12, 2020
[L10] X:7217mil Y:6406mil - P1V0 polygon creates multiple acid traps
#84
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[TSilk] Add text "HPC" and "LPC" to indicate the type of FMC slot.
#77
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[TSilk] "PCIe data" and "PCIe clock & SUPPLY" refers to what exactly? The connector above provides only power.
#76
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L10] X:5647mil Y:4087mil - sumoptimal polygon shape around P3V3_FMC pad
#83
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L10] X:5445mil Y:3854mil - possible acid trap
#82
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L1] J16 unnecessary, unused traces from S2, S3 pad
#78
· opened
Jul 06, 2020
by
Grzegorz Daniluk
CLOSED
1
updated
Jul 12, 2020
[L4] duplicate P5V_VME polygon on one more layer?
#80
· opened
Jul 06, 2020
by
Grzegorz Daniluk
0
updated
Jul 06, 2020
Remove J1 and J16 (stand-alone power port)
#3
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
3
updated
Jul 02, 2020
Documentation-related issues
#40
· opened
Apr 16, 2020
by
Tomasz Wlostowski
Ready for PCB layout review.
minor
0
updated
Jul 02, 2020
Stackup table
1 of 2 tasks completed
#67
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
0
updated
Jun 04, 2020
Reference plane continuity for differential pairs problems
10 of 10 tasks completed
#73
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
DRC check
#62
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
DDR reference plane continuity
#74
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
OHWR license on PCB should be newer
#70
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
Matched length between DDR address and data
#65
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
No matched net length within differential pair
#64
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
8 silkscreen strings are outside of the board
#72
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 04, 2020
DiffPairsRouting rule
#63
· opened
Jun 01, 2020
by
Paweł Kulik
1
updated
Jun 02, 2020
Vias under SMD pads should be unmasked
#66
· opened
Jun 01, 2020
by
Paweł Kulik
CLOSED
1
updated
Jun 02, 2020
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