... | @@ -15,7 +15,7 @@ tbd |
... | @@ -15,7 +15,7 @@ tbd |
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- V3.0 Bootloader bitstream (System FPGA, Xilinx BIT):
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- V3.0 Bootloader bitstream (System FPGA, Xilinx BIT):
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[svec-bootloader-v3-20140815.bit](https://www.ohwr.org/project/svec/uploads/bbb9abcd3ccc8047aa748fb0a8a9d2b9/svec-bootloader-v2-20140207.bit)
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[svec-bootloader-v3-20140815.bit](https://www.ohwr.org/project/svec/uploads/bbb9abcd3ccc8047aa748fb0a8a9d2b9/svec-bootloader-v2-20140207.bit)
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- V3.0 Bootloader bitstream (System FPGA, Intel HEX/MCS):
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- V3.0 Bootloader bitstream (System FPGA, Intel HEX/MCS):
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[svec-bootloader-v2-20140815.mcs](https://www.ohwr.org/project/svec/uploads/36d401e8996b5d8e431ab018554a487c/svec-bootloader-v2-20140207.mcs)
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[svec-bootloader-v3-20140815.mcs](https://www.ohwr.org/project/svec/uploads/36d401e8996b5d8e431ab018554a487c/svec-bootloader-v2-20140207.mcs)
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