Simple PXI express FMC Carrier Board (SPEXI)
Project description
The PXI express FMC Carrier Board (SPEXI) is the PXI express version of the SPEC board. It is an FMC carrier that can hold one FMC card and an SFP connector. On the PXI express side it has a 4-lane interface, while the FMC mezzanine slot uses a low-pin count connector. This board will be usable with most of the FMC cards designed within CERN’s OHR project (e.g. ADC cards, Fine Delay).
LabVIEW drivers are available for the FMC DEL 1ns 4cha delay and FMC TDC 1ns 5cha TDC mezzanine cards. These drivers do not support White Rabbit.
Spexi means "I observe, watch, look at." in Latin.
SPEXI v1
Main Features
- 4-lane PCIe (Gennum GN4124) obsolete component, not available anymore
- 1x Xilinx Spartan6 FPGA (XC6SLX150T-3FGG900C)
- FMC slot with low pin count (LPC) connector
- Vadj fixed to 2.5V
- FMC connectivity: all 34 differential pairs connected, 1 GTP transceiver with clock, 2 clock pairs, JTAG
- No dedicated clock signals from Carrier to FMC (only available on HPC pins)
- Simple clocking resources
- 1x 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs Si570)
- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core
- 1x low-jitter frequency synthesizer (TI CDCM61004, fixed configuration, Fout=125MHz, used by White Rabbit PTP core)
- On board memory
- 1x 2Gbit (256 MByte) DDR3 (MT41J128M16JT-125)
- 1x SPI 32Mbit flash PROM for multiboot FPGA powerup configuration, storage of the FPGA firmware or of critical data (M25P128-VMF6G)
- Miscellaneous
- on-board thermometer IC (DS18B20U+)
- unique 64-bit identifier (DS18B20U+)
- Front panel containing
- 1x Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver (WhiteRabbit support). 1.25 and 2.5 Gbps. Note: WR is not supported by the LabVIEW drivers.
- Programmable Red and Green LEDs
- FMC front panel
- Internal connectors
- 1x JTAG header for Xilinx programming during debugging
- 1x mini USB AB (USB-UART bridge)
- FPGA configuration. The FPGA can optionally be programmed from:
- GN4124 SPRIO interface (loaded by software driver at startup)
- JTAG header
- SPI 32Mbit flash PROM
- selectable by GN4124 GPIO. Default option would be loading via the SPI flash PROM (stand-alone applications).
- Debugging features
- mini USB connector
- 4 LEDs
- 2 buttons
- Optimised for cost
- 8-layer PCB
PXIe specific features
- PXI express form factor, 3U high, single slot
- Clock and synchronisation back plane signals
| PXI clock and synchronisation signals | PXI express clock and synchronisation signals |
|---|---|
| PXI_TRIG[0:7] | PXIe_DSTARA |
| PXI_CLK10 | PXIe_DSTARB |
| PXI_STAR | PXIe_DSTARC |
| PXI_LBL6 | PXIe_CLK100 |
| PXI_LBR6 | PXIe_SYNC100 |
Project information
- Official production documentation: EDMS EDA-02839
- CERN specific information
- Design Information
- Software
- Users
- Frequently Asked Questions
Since the SPEXI is a board which is based on the design of the SPEC, some of the documentation of the SPEC can also be used:
Releases
Hardware
- Official production documentation: EDMS EDA-02839
- Pre-release design documentation: SPEXI-V1.0.zip
FPGA examples (including the .ucf-file)
-
spexi_simpledemo.zip
The file spexi_simpledemo.zip contains a demo design and all the files including the .bit and .msc files which can be used to download this design to the SPEXI using Xilinx iMPACT and the download cable, or use the download path via the Gennum GN4124. This design contains the interface to the Gennum GN4124, an I2C master to access the FMC board eeprom, a carrier control and status register to get some information of the SPEXI carrier, and a GPIO register to access the four LEDs and the two buttons.
To download the .mcs file into the SPI memory (M25P128) you will need to configure iMPACT to access the SPI flash memory connector to the Spartan-6 150T. -
spexi_golden.zip
The file spexi_golden.zip contains the same design as spexi_simpledemo.zip but does not contain the GPIO register for the LEDs and buttons. This design is used to be able to get the first information from the SPEXI and the FMC to be able to determine which other FMC specific FPGA design could be loaded safely. -
spexi_pts.zip
The file spexi_pts.zip contains the complete set of VHDL/FPGA designs and corresponding phyton files for the Production Test Suite. This PTS is used to test the boards functionally after manufacturing. Because of this the designs also contain several examples of how to connect to the other interfaces on the SPEXI carrier.
Contacts
Commercial producers
- SPEXI INCAA Computers, Netherlands.
General question about project
- Adriaan Rijllart - CERN - project initiator
- Erik van der Bij - CERN
Status
| Date | Event |
|---|---|
| 06-04-2011 | First ideas for project. |
| 17-01-2012 | Price Enquiry sent out for design by industry based on SPEC board. |
| 12-03-2012 | Order for design and two pre-series boards placed with INCAA. Delivery by 12-07-2012. |
| 16-05-2012 | Schematics being made. |
| 29-05-2012 | Removed SATA connectors and stand-alone possibility from specification. |
| 17-08-2012 | V0 Schematics and PCB uploaded and available for review |
| 30-08-2012 | First review V0 Review20120830. |
| 04-10-2012 | Second schematics review V0. |
| 19-11-2012 | V0-2 ready for review. |
| 07-11-2012 | V0-2 reviewed. Only one single minor comment. |
| 21-01-2013 | Bare PCBs ready for assembly of components. |
| 07-02-2013 | PCBs should be assembled by 22 February 2013. |
| 07-03-2013 | Assembled PCB available. Production Test Software being written based on SVEC PTS. |
| 28-06-2013 | V1-0 files being finalised. Ready in a week. |
| 02-07-2013 | V1-0 files ready for verification and cleanup by CERN design office. |
| 30-07-2013 | V1-0 files reviewed. Main comments about component spacing. Will clean up design. |
| 28-08-2013 | Added PROM to design and cleaned up files. Will be checked by CERN design office. Ordered 10 boards. |
| 03-09-2012 | Prototype SPEXI board received (from base layout). |
| 25-09-2013 | Design V1-0 checked and improved. Released for production. |
| 08-10-2013 | Driver Fine Delay card ported from SPEC to SPEXI. Ready for testing. TDC driver will be ported next. |
| 03-12-2013 | Labview Driver available for FMC DEL 1ns 4cha and FMC TDC 1ns 5cha. |
| 30-01-2014 | Series production of 10 cards received at CERN. |
| 30-04-2014 | Ordered 25 boards. |
| 04-06-2014 | Airbus Defence&Space: Evaluating SPEXI for use as backbone for future test systems for space electronics. |
| 23-07-2014 | Astrium GmbH, Germany, will use the SPEXI with the 24 bit ADC for measurements using PT1000. |
| 31-07-2014 | Received the 25 boards. |
| 04-09-2015 | 4 SPEXI boards with FMC-DEL cards have been deployed in the kicker control systems at CERN (LEIR and others). |
| 08-09-2015 | A SPEXI boards with a FMC-TDC card is under study to be used. |
| 22-04-2016 | Airbus Defence&Space is using the SPEXI as their backbone in test systems for space electronics. |
| 03-10-2016 | The Ecole d'Ingénieurs in Fribourg will use the SPEXI |
| 29-03-2017 | In SM18 the SPEXI will be used with a TDC for magnet quench trigger time stamping |
| 08-09-2017 | Labview VISA driver implements White Rabbit for FMC TDC 1ns 5cha hardware |
Erik van der Bij, Adriaan Rijllart - 8 September 2017