Review20120830

SPEXI Review 30-08-2012

Tom Wlostowski - CERN - 30 August 2012
Reviewed Design: https://www.ohwr.org/project/spexi/uploads/d7803ca7e5c12367c5c3195ef96ade11/SPEXI-V0-0.zip
(17/08/2012 11:07 16.7 MB 7 65c12a21d094e4e29d40cf254dfca131)

General:

• DrawnBy: should be CERN on the sheets that were simply copied from the SPEC design.
• note: I didn't check the PXIe part, I must read the PXI standard first :)

fpga_io_fmc:

• FMC LVDS lines are seriously messed up:

In Spartan-6 FPGAs (see UG381, page 28), LVDS outputs are supported only on banks 0 and 2,
while the majority of the lines is connected to banks 1 and 3 (FMC standard assumes all
pairs are bidirectional). Reroute them to banks 0 or 2.

• Redesign all LAx differential pair connections.

- Only use banks 0 or 2.
- Connect LA02-LA15 to one half-bank (and LA00/LA16 to the GCLK input
of that half-bank)
- Connect LA19-LA33 to one half-bank (and LA17/LA18 to the GCLK input
of that half-bank)
- All FMC lines fit in a single bank 0. In case of bank 2 routing
(easier - no need to redo the gennum part of the PCB), connect LA32 and
33 to bank 0.

• Redesign Gennum connections (move to bank 1/3) to reduce the impact of
  banks 0/2 on GTP performance, according to Xilinx note:
  http://www.xilinx.com/support/answers/35237.htm.
  - PCB routing : swap gennum with the oscillators (?)

• See attached file Spexi_pins.ods

fpga_io_pcie:

• move to bank 1/3
• put P2L_DATA8 in the upper half of the bank
• move P2L_CLK to the upper half of the bank

jtag&config:

• 4 MB (32 Mbit) flash can store only one bitstream (3.3MB for
  LX100T). Consider using a larger memory (M25P128, as in the SVEC).

PCB (incomplete):

• clearance between differential pairs seems too low (in some cases,
  even smaller than the coupling distance - e.g. the FMC lines).
  We use 3x coupling distance rule at CERN. Consider applying it at
  least to the multi-gigabit signals (PCIe, SFP, DP0)
• vias under BGAs without solder mask tenting
• use wider thermal breakouts for high current pads (coils/caps in
  the power supply)
• vias on BGA pads (FPGA pin AA24, lots of DDR3 pads, there are more)
• it makes no sense to impedance-match the very short traces between
  DDR3 pads and their termination resistors on the top
  layer (e.g. R67).
• avoid acute angle pad exits (see R83)
• newer version of Altium (10.391.22084) reports 22 DRC errors (add
  ignore constraints)
• 0.1mm length matching constraint on PXIe lines is a bit exaggerated...

Files

• Spexi_pins.ods