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# Review20120830
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# SPEXI Review 30-08-2012
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Tom Wlostowski - CERN - 30 August 2012
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Reviewed Design:
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https://www.ohwr.org/project/spexi/uploads/d7803ca7e5c12367c5c3195ef96ade11/SPEXI-V0-0.zip
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(17/08/2012 11:07 16.7 MB 7 65c12a21d094e4e29d40cf254dfca131)
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## General:
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- DrawnBy: should be CERN on the sheets that were simply copied from
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the SPEC design.
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- note: I didn't check the PXIe part, I must read the PXI standard
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first :)
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## fpga\_io\_fmc:
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- FMC LVDS lines are seriously messed up:
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In Spartan-6 FPGAs (see UG381, page 28), LVDS outputs are supported only
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on banks 0 and 2,
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while the majority of the lines is connected to banks 1 and 3 (FMC
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standard assumes all
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pairs are bidirectional). Reroute them to banks 0 or 2.
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- Redesign all LAx differential pair connections.
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\- Only use banks 0 or 2.
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\- Connect LA02-LA15 to one half-bank (and LA00/LA16 to the GCLK input
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of that half-bank)
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\- Connect LA19-LA33 to one half-bank (and LA17/LA18 to the GCLK input
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of that half-bank)
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\- All FMC lines fit in a single bank 0. In case of bank 2 routing
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(easier - no need to redo the gennum part of the PCB), connect LA32
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and
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33 to bank 0.
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- Redesign Gennum connections (move to bank 1/3) to reduce the impact
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of
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banks 0/2 on GTP performance, according to Xilinx note:
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http://www.xilinx.com/support/answers/35237.htm.
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\- PCB routing : swap gennum with the oscillators (?)
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*See attached file Spexi\_pins.ods**
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## fpga\_io\_pcie:
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- move to bank 1/3
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- put P2L\_DATA8 in the upper half of the bank
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- move P2L\_CLK to the upper half of the bank
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## jtag\&config:
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- 4 MB (32 Mbit) flash can store only one bitstream (3.3MB for
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LX100T). Consider using a larger memory (M25P128, as in the SVEC).
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## PCB (incomplete):
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- clearance between differential pairs seems too low (in some cases,
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even smaller than the coupling distance - e.g. the FMC lines).
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We use 3x coupling distance rule at CERN. Consider applying it at
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least to the multi-gigabit signals (PCIe, SFP, DP0)
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- vias under BGAs without solder mask tenting
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- use wider thermal breakouts for high current pads (coils/caps in
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the power supply)
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- vias on BGA pads (FPGA pin AA24, lots of DDR3 pads, there are more)
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- it makes no sense to impedance-match the very short traces between
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DDR3 pads and their termination resistors on the top
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layer (e.g. R67).
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- avoid acute angle pad exits (see R83)
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- newer version of Altium (10.391.22084) reports 22 DRC errors (add
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ignore constraints)
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- 0.1mm length matching constraint on PXIe lines is a bit
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exaggerated...
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-----
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### Files
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* [Spexi_pins.ods](/uploads/e7ed292b75576b739f1dea286ce53812/Spexi_pins.ods) |
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\ No newline at end of file |