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# PXI express FMC Carrier Board (SPEXI)
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## Project description
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The PXI express FMC Carrier Board (SPEXI) is the PXI express version of
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the [SPEC board](https://www.ohwr.org/project/spec). It is an FMC
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carrier that can hold one FMC card and an SFP connector. On the PXI
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express side it has a 4-lane interface, while the FMC mezzanine slot
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uses a low-pin count connector. This board is optimised for cost and
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will be usable with most of the FMC cards designed within CERN’s OHR
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project (e.g. ADC cards, Fine Delay).
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Spexi means *"I observe, watch, look at."* in Latin.
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## Main Features
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\* 4-lane PCIe (Gennum GN4124)
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\* FMC slot with low pin count (LPC) connector
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o Vadj fixed to 2.5V
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o No dedicated clock signals from Carrier to FMC (only available on HPC
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pins)
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o LPC cheaper than HPC and also easier to mount
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o FMC connectivity: all 34 differential pairs connected, 1 GTP
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transceiver with clock, 2 clock pairs, JTAG
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\* 1 Xilinx Spartan6 FPGA (XC6SLX45T) or equivalent
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\* Simple clocking resources
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o 1 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs Si570)
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o 1 25 MHz TCXO controlled by a DAC with SPI interface (AD5662)
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o 1 20 MHz VCXO controlled by a DAC with SPI interface (AD5662)
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o 1 low-jitter frequency synthesizer (TI CDCM61004, fixed configuration,
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Fout=125MHz)
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\* On board memory
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o A 2Gbit DDR3
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o 1 SPI 32Mbit flash PROM for multiboot FPGA powerup configuration,
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storage of the FPGA firmware or of critical data
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\* Front panel containing
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o 1 Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver
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([WhiteRabbit](https://www.ohwr.org/project/white-rabbit) support)
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o Programmable LED
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o FMC front panel
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\* Internal connectors
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o 1 JTAG header for Xilinx programming during debugging
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o 2 SATA connectors
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o 1 mini USB AB (USB-UART bridge)
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\* FPGA configuration. The FPGA can optionally be programmed from:
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o GN4124 SPRIO interface (loaded by software driver at startup)
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o JTAG header
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o SPI 32Mbit flash PROM
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o selectable by GN4124 GPIO. Default option would be loading via the SPI
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flash PROM (stand-alone applications).
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\* Stand-alone features
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o External 12V power supply connector
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o mini USB connector
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o 4 LEDs
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o 2 buttons
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\* Optimised for cost
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## PXIe specific features
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\* PXI express form factor, 3U high, single slot
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\* Clock and synchronisation back plane signals
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>PXI clock and synchronisation signals</strong></td>
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<td><strong>PXI express clock and synchronisation signals</strong></td>
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</tr>
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<tr class="even">
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<td>PXI_TRIG[0:7]</td>
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<td>PXIe_DSTARA</td>
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</tr>
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<tr class="odd">
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<td>PXI_CLK10</td>
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<td>PXIe_DSTARB</td>
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</tr>
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<tr class="even">
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<td>PXI_STAR</td>
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<td>PXIe_DSTARC</td>
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</tr>
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<tr class="odd">
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<td>PXI_LBL6</td>
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<td>PXIe_CLK100</td>
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</tr>
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<tr class="even">
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<td>PXI_LBR6</td>
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<td>PXIe_SYNC100</td>
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</tr>
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</tbody>
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</table>
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-----
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## Project information
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- Official production documentation:
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- [Users](Users)
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-----
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## Releases
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-----
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## Contacts
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### Commercial producers
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- none yet
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### General question about project
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
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-----
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## Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>06-04-2011</td>
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<td>First ideas for project.</td>
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</tr>
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<tr class="odd">
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<td>17-01-2012</td>
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<td>Price Enquiry sent out for design by industry based on SPEC board.</td>
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</tr>
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</tbody>
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</table>
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-----
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Erik van der Bij, Adriaan Rijllart - 23 January 2012
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