... | @@ -6,9 +6,9 @@ The PXI express FMC Carrier Board (SPEXI) is the PXI express version of |
... | @@ -6,9 +6,9 @@ The PXI express FMC Carrier Board (SPEXI) is the PXI express version of |
|
the [SPEC board](https://www.ohwr.org/project/spec). It is an FMC
|
|
the [SPEC board](https://www.ohwr.org/project/spec). It is an FMC
|
|
carrier that can hold one FMC card and an SFP connector. On the PXI
|
|
carrier that can hold one FMC card and an SFP connector. On the PXI
|
|
express side it has a 4-lane interface, while the FMC mezzanine slot
|
|
express side it has a 4-lane interface, while the FMC mezzanine slot
|
|
uses a low-pin count connector. This board is optimised for cost and
|
|
uses a low-pin count connector. This board will be usable with most of
|
|
will be usable with most of the FMC cards designed within CERN’s OHR
|
|
the FMC cards designed within CERN’s OHR project (e.g. ADC cards, Fine
|
|
project (e.g. ADC cards, Fine Delay).
|
|
Delay).
|
|
|
|
|
|
*Spexi* means *"I observe, watch, look at."* in Latin.
|
|
*Spexi* means *"I observe, watch, look at."* in Latin.
|
|
|
|
|
... | @@ -22,7 +22,7 @@ pins) |
... | @@ -22,7 +22,7 @@ pins) |
|
o LPC cheaper than HPC and also easier to mount
|
|
o LPC cheaper than HPC and also easier to mount
|
|
o FMC connectivity: all 34 differential pairs connected, 1 GTP
|
|
o FMC connectivity: all 34 differential pairs connected, 1 GTP
|
|
transceiver with clock, 2 clock pairs, JTAG
|
|
transceiver with clock, 2 clock pairs, JTAG
|
|
\* 1 Xilinx Spartan6 FPGA (XC6SLX45T) or equivalent
|
|
\* 1 Xilinx Spartan6 FPGA (XC6SLX150T-3FGG900C)
|
|
\* Simple clocking resources
|
|
\* Simple clocking resources
|
|
o 1 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs Si570)
|
|
o 1 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs Si570)
|
|
o 1 25 MHz TCXO controlled by a DAC with SPI interface (AD5662)
|
|
o 1 25 MHz TCXO controlled by a DAC with SPI interface (AD5662)
|
... | @@ -160,10 +160,14 @@ o 2 buttons |
... | @@ -160,10 +160,14 @@ o 2 buttons |
|
<td>19-11-2012</td>
|
|
<td>19-11-2012</td>
|
|
<td>V0-2 ready for review.</td>
|
|
<td>V0-2 ready for review.</td>
|
|
</tr>
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td>07-11-2012</td>
|
|
|
|
<td>V0-2 reviewed. Only one single minor comment.</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</tbody>
|
|
</table>
|
|
</table>
|
|
|
|
|
|
-----
|
|
-----
|
|
|
|
|
|
Erik van der Bij, Adriaan Rijllart - 30 November 2012
|
|
Erik van der Bij, Adriaan Rijllart - 7 December 2012
|
|
|
|
|