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@@ -14,44 +14,46 @@ Delay).
 
 ## Main Features
 
-\* 4-lane PCIe (Gennum GN4124)  
-\* FMC slot with low pin count (LPC) connector  
-o Vadj fixed to 2.5V  
-o No dedicated clock signals from Carrier to FMC (only available on HPC
-pins)  
-o LPC cheaper than HPC and also easier to mount  
-o FMC connectivity: all 34 differential pairs connected, 1 GTP
+  - 4-lane PCIe (Gennum GN4124)
+  - FMC slot with low pin count (LPC) connector
+      - Vadj fixed to 2.5V
+      - No dedicated clock signals from Carrier to FMC (only available
+        on HPC pins)
+      - LPC cheaper than HPC and also easier to mount
+      - FMC connectivity: all 34 differential pairs connected, 1 GTP
         transceiver with clock, 2 clock pairs, JTAG
-\* 1 Xilinx Spartan6 FPGA (XC6SLX150T-3FGG900C)  
-\* Simple clocking resources  
-o 1 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs Si570)  
-o 1 25 MHz TCXO controlled by a DAC with SPI interface (AD5662)  
-o 1 20 MHz VCXO controlled by a DAC with SPI interface (AD5662)  
-o 1 low-jitter frequency synthesizer (TI CDCM61004, fixed configuration,
-Fout=125MHz)  
-\* On board memory  
-o A 2Gbit DDR3  
-o 1 SPI 32Mbit flash PROM for multiboot FPGA powerup configuration,
-storage of the FPGA firmware or of critical data  
-\* Front panel containing  
-o 1 Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver
-([WhiteRabbit](https://www.ohwr.org/project/white-rabbit) support)  
-o Programmable LED  
-o FMC front panel  
-\* Internal connectors  
-o 1 JTAG header for Xilinx programming during debugging  
-o 1 mini USB AB (USB-UART bridge)  
-\* FPGA configuration. The FPGA can optionally be programmed from:  
-o GN4124 SPRIO interface (loaded by software driver at startup)  
-o JTAG header  
-o SPI 32Mbit flash PROM  
-o selectable by GN4124 GPIO. Default option would be loading via the SPI
-flash PROM (stand-alone applications).  
-\* Debugging features  
-o mini USB connector  
-o 4 LEDs  
-o 2 buttons  
-\* Optimised for cost
+  - 1 Xilinx Spartan6 FPGA (XC6SLX150T-3FGG900C) 
+  - Simple clocking resources
+      - 1 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs Si570)
+      - 1 25 MHz TCXO controlled by a DAC with SPI interface (AD5662)
+      - 1 20 MHz VCXO controlled by a DAC with SPI interface (AD5662)
+      - 1 low-jitter frequency synthesizer (TI CDCM61004, fixed
+        configuration, Fout=125MHz)
+  - On board memory
+      - A 2Gbit DDR3
+      - 1 SPI 32Mbit flash PROM for multiboot FPGA powerup
+        configuration, storage of the FPGA firmware or of critical data 
+  - Front panel containing
+      - 1 Small Formfactor Pluggable (SFP) cage for fibre-optic
+        transceiver
+        ([WhiteRabbit](https://www.ohwr.org/project/white-rabbit)
+        support) 
+      - Programmable LED
+      - FMC front panel
+  - Internal connectors
+      - 1 JTAG header for Xilinx programming during debugging
+      - 1 mini USB AB (USB-UART bridge)
+  - FPGA configuration. The FPGA can optionally be programmed from:
+      - GN4124 SPRIO interface (loaded by software driver at startup)
+      - JTAG header
+      - SPI 32Mbit flash PROM
+      - selectable by GN4124 GPIO. Default option would be loading via
+        the SPI flash PROM (stand-alone applications).
+  - Debugging features
+      - mini USB connector
+      - 4 LEDs
+      - 2 buttons
+  - Optimised for cost
 
 ## PXIe specific features