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Simple PCIe FMC carrier SPEC
Commit de80bdd9 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Merge branch 'feature/hdl/top_level_cleanup' into develop

parents 903f594d 9288616d
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hdl/rtl/spec_base_wr.vhd
View file @ de80bdd9
......@@ -301,7 +301,7 @@ entity spec_base_wr is
-- Addresses 0-0x1fff are not available (used by the carrier).
-- This is a pipelined wishbone with byte granularity.
app_wb_o : out t_wishbone_master_out;
app_wb_i : in t_wishbone_master_in;
app_wb_i : in t_wishbone_master_in := c_DUMMY_WB_MASTER_IN;
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
sim_wb_o : out t_wishbone_slave_out
......
hdl/syn/dma_test/Manifest.py → hdl/syn/golden-100T/Manifest.py
View file @ de80bdd9
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_device = "xc6slx100t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_dma_test.xise"
syn_tool = "ise"
syn_top = "spec_dma_test"
syn_project = "spec_golden-100T.xise"
syn_tool = "ise"
syn_top = "spec_golden"
spec_base_ucf = ['onewire', 'spi', 'ddr3']
board = "spec"
spec_base_ucf = ['ddr3']
ctrls = ["bank3_32b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/dma_test", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"../../top/golden",
"../../syn/common",
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
......
hdl/syn/golden/Manifest.py → hdl/syn/golden-150T/Manifest.py
View file @ de80bdd9
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden.xise"
syn_tool = "ise"
syn_top = "spec_golden"
syn_project = "spec_golden-150T.xise"
syn_tool = "ise"
syn_top = "spec_golden"
spec_base_ucf = ['onewire', 'spi', 'ddr3']
spec_base_ucf = ['onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
ctrls = ["bank3_32b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/golden", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"../../top/golden",
"../../syn/common",
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
hdl/syn/golden_wr/Manifest.py → hdl/syn/golden-45T/Manifest.py
View file @ de80bdd9
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"
syn_tool = "ise"
syn_top = "spec_golden_wr"
syn_project = "spec_golden-45T.xise"
syn_tool = "ise"
syn_top = "spec_golden"
spec_base_ucf = ['onewire', 'spi', 'ddr3']
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
ctrls = ["bank3_32b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/golden_wr", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"../../top/golden",
"../../syn/common",
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
hdl/syn/golden_wr-150T/Manifest.py deleted 100644 → 0
View file @ 903f594d
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"
syn_tool = "ise"
syn_top = "spec_golden_wr"
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden_wr", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/golden_wr/syn_extra_steps.tcl deleted 100644 → 0
View file @ 903f594d
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/syn/full/Manifest.py → hdl/syn/wr_example/Manifest.py
View file @ de80bdd9
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_full.xise"
syn_tool = "ise"
syn_top = "spec_full"
syn_project = "spec_base_wr_example.xise"
syn_tool = "ise"
syn_top = "spec_base_wr_example"
spec_base_ucf = ['wr', 'onewire', 'spi', 'ddr3']
board = "spec"
ctrls = ["bank3_64b_32b" ]
ctrls = ["bank3_32b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/full", "../../syn/common"
],
"../../top/wr_example",
"../../syn/common",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
......@@ -31,6 +28,10 @@ modules = {
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
......
hdl/testbench/dma_test/Manifest.py → hdl/testbench/golden/Manifest.py
View file @ de80bdd9
......@@ -25,14 +25,8 @@ files = [
modules = {
"local" : [
"../../top/dma_test",
"../../top/golden",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
......
hdl/testbench/dma_test/main.sv → hdl/testbench/golden/main.sv
View file @ de80bdd9
......@@ -32,7 +32,7 @@ module main;
// 125Mhz
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
spec_dma_test
spec_golden
#(
.g_SIMULATION(1)
)
......@@ -167,32 +167,6 @@ module main;
typedef virtual IGN4124PCIMaster vIGN4124PCIMaster;
task dma_read_pattern(vIGN4124PCIMaster i_gn4124);
int i;
uint64_t val, expected;
CBusAccessor acc;
acc = i_gn4124.get_accessor();
acc.set_default_xfer_size(4);
// Read pattern from device memory
dma_xfer(acc, 'h20000000, 'h0, 4 * 'h20, RD);
// Verify pattern
for (i = 'h00; i < 'h20; i++)
begin
expected = i+1;
expected |= (i+1) << 8;
expected |= (i+1) << 16;
expected |= (i+1) << 24;
i_gn4124.host_mem_read(i*4, val);
if (val != expected)
$fatal(1, "<%t> READ-BACK ERROR at host address 0x%x: expected 0x%8x, got 0x%8x",
$realtime, i*4, expected, val);
end
endtask // dma_read_pattern
task dma_test(vIGN4124PCIMaster i_gn4124,
input uint32_t word_count);
......@@ -272,8 +246,6 @@ module main;
#10us;
dma_read_pattern(vi_gn4124);
for (i = 2; i < 13; i++)
begin
#1us;
......
hdl/top/full/Manifest.py deleted 100644 → 0
View file @ 903f594d
files = ["spec_full.vhd"]
modules = {'local': ["../../rtl"]}
hdl/top/full/spec_full.vhd deleted 100644 → 0
View file @ 903f594d
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_full
--
-- description: SPEC "full" design, with access to all peripherals and features
-- of the carrier board.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_full is
generic (
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : boolean := False
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
---------------------------------------------------------------------------
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe_i : in std_logic; -- Receive Frame
gn_p2l_valid_i : in std_logic; -- Receive Data Valid
gn_p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe_o : out std_logic; -- Transmit Data Frame
gn_l2p_valid_o : out std_logic; -- Transmit Data Valid
gn_l2p_edb_o : out std_logic; -- Packet termination and discard
gn_l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error_i : in std_logic; -- Transmit Error
gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio_b : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- Miscellanous SPEC pins
---------------------------------------------------------------------------
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
button1_n_i : in std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
-- DDR3
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic
);
end entity spec_full;
architecture top of spec_full is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
begin
inst_spec_base: entity work.spec_base_wr
generic map (
g_with_vic => True,
g_with_onewire => False,
g_with_spi => False,
g_with_ddr => True,
g_dpram_initf => g_dpram_initf,
g_simulation => g_simulation
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
-- Everything is handled by the carrier.
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
end architecture top;
hdl/top/golden/Manifest.py
View file @ de80bdd9
files = ["spec_golden.vhd"]
modules = {'local': ["../../rtl"]}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"spec_golden.vhd",
]
modules = {
"local" : [
"../../rtl",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
hdl/top/golden/spec_golden.vhd
View file @ de80bdd9
......@@ -9,7 +9,7 @@
-- description: SPEC golden design, without WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
-- Copyright CERN 2019-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
......@@ -24,132 +24,154 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
entity spec_golden is
generic (
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : boolean := FALSE
);
port (
-- Global ports
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
gn_RST_N_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
gn_GPIO_b : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
gn_P2L_RDY_o : out std_logic; -- Rx Buffer Full Flag
gn_P2L_CLK_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_P2L_CLK_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_P2L_DATA_i : in std_logic_vector(15 downto 0); -- Parallel receive data
gn_P2L_DFRAME_i : in std_logic; -- Receive Frame
gn_P2L_VALID_i : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
gn_P_WR_REQ_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_P_WR_RDY_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_RX_ERROR_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_L2P_DATA_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
gn_L2P_DFRAME_o : out std_logic; -- Transmit Data Frame
gn_L2P_VALID_o : out std_logic; -- Transmit Data Valid
gn_L2P_CLK_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_L2P_CLK_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_L2P_EDB_o : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
gn_L2P_RDY_i : in std_logic; -- Tx Buffer Full Flag
gn_L_WR_RDY_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_P_RD_D_RDY_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_TX_ERROR_i : in std_logic; -- Transmit Error
gn_VC_RDY_i : in std_logic_vector(1 downto 0); -- Channel ready
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Font panel LEDs
-- LED_RED : out std_logic;
-- LED_GREEN : out std_logic;
button1_n_i : in std_logic;
-- GN4124
gn_rst_n_i : in std_logic;
gn_p2l_clk_n_i : in std_logic;
gn_p2l_clk_p_i : in std_logic;
gn_p2l_rdy_o : out std_logic;
gn_p2l_dframe_i : in std_logic;
gn_p2l_valid_i : in std_logic;
gn_p2l_data_i : in std_logic_vector(15 downto 0);
gn_p_wr_req_i : in std_logic_vector(1 downto 0);
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0);
gn_rx_error_o : out std_logic;
gn_l2p_clk_n_o : out std_logic;
gn_l2p_clk_p_o : out std_logic;
gn_l2p_dframe_o : out std_logic;
gn_l2p_valid_o : out std_logic;
gn_l2p_edb_o : out std_logic;
gn_l2p_data_o : out std_logic_vector(15 downto 0);
gn_l2p_rdy_i : in std_logic;
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0);
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0);
gn_tx_error_i : in std_logic;
gn_vc_rdy_i : in std_logic_vector(1 downto 0);
gn_gpio_b : inout std_logic_vector(1 downto 0);
-- PCB version and reset button
pcbrev_i : in std_logic_vector(3 downto 0);
button1_n_i : in std_logic;
-- I2C to the FMC
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i : in std_logic;
-- DDR3
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic;
-- Onewire
onewire_b : inout std_logic;
-- SPI
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end spec_golden;
architecture rtl of spec_golden is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
architecture arch of spec_golden is
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
begin
inst_spec_base: entity work.spec_base_wr
inst_spec_base : entity work.spec_base_wr
generic map (
g_WITH_VIC => True,
g_WITH_ONEWIRE => True,
g_WITH_SPI => True,
g_WITH_DDR => False,
g_WITH_WR => False,
g_simulation => False
)
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => TRUE,
g_WITH_SPI => TRUE,
g_WITH_DDR => TRUE,
g_DDR_DATA_SIZE => 32,
g_WITH_WR => FALSE,
g_SIMULATION => g_SIMULATION
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
-- Everything is handled by the carrier.
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
end rtl;
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
button1_n_i => button1_n_i,
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o
);
end architecture arch;
hdl/top/golden_wr/Manifest.py deleted 100644 → 0
View file @ 903f594d
files = ["spec_golden_wr.vhd"]
modules = {'local': ["../../rtl"]}
hdl/top/golden_wr/spec_golden_wr.vhd deleted 100644 → 0
View file @ 903f594d
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_golden_wr
--
-- description: SPEC golden design, with WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_golden_wr is
generic (
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : boolean := False
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
---------------------------------------------------------------------------
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe_i : in std_logic; -- Receive Frame
gn_p2l_valid_i : in std_logic; -- Receive Data Valid
gn_p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe_o : out std_logic; -- Transmit Data Frame
gn_l2p_valid_o : out std_logic; -- Transmit Data Valid
gn_l2p_edb_o : out std_logic; -- Packet termination and discard
gn_l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error_i : in std_logic; -- Transmit Error
gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio_b : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- Miscellanous SPEC pins
---------------------------------------------------------------------------
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
button1_n_i : in std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic
);
end entity spec_golden_wr;
architecture top of spec_golden_wr is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
begin
inst_spec_base: entity work.spec_base_wr
generic map (
g_WITH_VIC => True,
g_WITH_ONEWIRE => False,
g_WITH_SPI => False,
g_WITH_DDR => False,
g_WITH_WR => True,
g_dpram_initf => g_dpram_initf,
g_simulation => g_simulation
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
-- Everything is handled by the carrier.
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
end architecture top;
hdl/top/dma_test/Manifest.py → hdl/top/wr_example/Manifest.py
View file @ de80bdd9
files = ["spec_dma_test.vhd"]
files = ["spec_base_wr_example.vhd"]
modules = {'local': ["../../rtl"]}
hdl/top/dma_test/spec_dma_test.vhd → hdl/top/wr_example/spec_base_wr_example.vhd
View file @ de80bdd9
......@@ -4,18 +4,12 @@
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_dma_test
-- unit name: spec_base_wr_example
--
-- description: A bitstream for testing DMA with a dummy application that pre-
-- loads the first 32 words (128 bytes) of the DDR with a predefined pattern:
--
-- 0x00: 0x01010101
-- 0x04: 0x02020202
-- ...
-- 0x7c: 0x20202020
-- description: Example instantiation of SPEC base with White Rabbit.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2020
-- Copyright CERN 2019-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
......@@ -32,60 +26,59 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.wishbone_pkg.all;
entity spec_base_wr_example is
entity spec_dma_test is
generic (
g_SIMULATION : boolean := FALSE
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : boolean := FALSE
);
port (
-- Global ports
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
-- From GN4124 Local bus
gn_rst_n_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe_i : in std_logic; -- Receive Frame
gn_p2l_valid_i : in std_logic; -- Receive Data Valid
gn_p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe_o : out std_logic; -- Transmit Data Frame
gn_l2p_valid_o : out std_logic; -- Transmit Data Valid
gn_l2p_edb_o : out std_logic; -- Packet termination and discard
gn_l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error_i : in std_logic; -- Transmit Error
gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio_b : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
clk_20m_vcxo_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
-- GN4124
gn_rst_n_i : in std_logic;
gn_p2l_clk_n_i : in std_logic;
gn_p2l_clk_p_i : in std_logic;
gn_p2l_rdy_o : out std_logic;
gn_p2l_dframe_i : in std_logic;
gn_p2l_valid_i : in std_logic;
gn_p2l_data_i : in std_logic_vector(15 downto 0);
gn_p_wr_req_i : in std_logic_vector(1 downto 0);
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0);
gn_rx_error_o : out std_logic;
gn_l2p_clk_n_o : out std_logic;
gn_l2p_clk_p_o : out std_logic;
gn_l2p_dframe_o : out std_logic;
gn_l2p_valid_o : out std_logic;
gn_l2p_edb_o : out std_logic;
gn_l2p_data_o : out std_logic_vector(15 downto 0);
gn_l2p_rdy_i : in std_logic;
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0);
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0);
gn_tx_error_i : in std_logic;
gn_vc_rdy_i : in std_logic_vector(1 downto 0);
gn_gpio_b : inout std_logic_vector(1 downto 0);
-- PCB version and reset button
pcbrev_i : in std_logic_vector(3 downto 0);
button1_n_i : in std_logic;
-- I2C to the FMC
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i : in std_logic;
-- DDR3
-- DDR3
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
......@@ -103,25 +96,53 @@ entity spec_dma_test is
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic
ddr_we_n_o : out std_logic;
-- Onewire
onewire_b : inout std_logic;
-- SPI
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
-- UART
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- SPI interface to DACs
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
-- SFP I/O for transceiver
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic
);
end spec_dma_test;
architecture arch of spec_dma_test is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
signal wb_ddr_out : t_wishbone_master_out;
signal wb_ddr_in : t_wishbone_master_in;
end entity spec_base_wr_example;
type fsm_state_type is (S_IDLE, S_WRITE, S_DONE);
signal fsm_current_state : fsm_state_type;
architecture arch of spec_base_wr_example is
begin
inst_spec_base : entity work.spec_base_wr
generic map (
g_WITH_VIC => TRUE,
......@@ -129,7 +150,8 @@ begin
g_WITH_SPI => FALSE,
g_WITH_DDR => TRUE,
g_DDR_DATA_SIZE => 32,
g_WITH_WR => FALSE,
g_WITH_WR => TRUE,
g_DPRAM_INITF => g_DPRAM_INITF,
g_SIMULATION => g_SIMULATION
)
port map (
......@@ -157,101 +179,56 @@ begin
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
pcbrev_i => pcbrev_i,
button1_n_i => button1_n_i,
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
ddr_dma_wb_cyc_i => wb_ddr_out.cyc,
ddr_dma_wb_stb_i => wb_ddr_out.stb,
ddr_dma_wb_adr_i => wb_ddr_out.adr,
ddr_dma_wb_sel_i => wb_ddr_out.sel,
ddr_dma_wb_we_i => wb_ddr_out.we,
ddr_dma_wb_dat_i => wb_ddr_out.dat,
ddr_dma_wb_ack_o => wb_ddr_in.ack,
ddr_dma_wb_stall_o => wb_ddr_in.stall,
ddr_dma_wb_dat_o => wb_ddr_in.dat,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
spi_miso_i => '0',
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
p_fsm : process (clk_sys_62m5) is
variable pattern : unsigned(7 downto 0) := (others => '0');
begin -- process p_fsm
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
fsm_current_state <= S_IDLE;
pattern := (others => '0');
wb_ddr_out.adr <= (others => '0');
wb_ddr_out.dat <= (others => '0');
wb_ddr_out.cyc <= '0';
wb_ddr_out.stb <= '0';
else
wb_ddr_out.sel <= "1111";
wb_ddr_out.we <= '1';
case fsm_current_state is
when S_IDLE =>
wb_ddr_out.cyc <= '1';
fsm_current_state <= S_WRITE;
when S_WRITE =>
if wb_ddr_in.stall = '0' then
pattern := pattern + 1;
wb_ddr_out.cyc <= '1';
wb_ddr_out.stb <= '1';
wb_ddr_out.dat <= std_logic_vector(pattern & pattern & pattern & pattern);
wb_ddr_out.adr(7 downto 0) <= std_logic_vector(pattern - 1);
if pattern = 32 then
fsm_current_state <= S_DONE;
end if;
end if;
when S_DONE =>
if wb_ddr_in.stall = '0' then
wb_ddr_out.cyc <= '0';
wb_ddr_out.stb <= '0';
end if;
end case;
end if;
end if;
end process p_fsm;
end architecture arch;
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