spec_base_wr: automatically set the g_BANK_PORT_SELECT generic.

d5576038 · Tristan Gingold · Federico Vaga · 57fbbf01 · d5576038
Commit d5576038 authored Sep 18, 2019 by Tristan Gingold Committed by Federico Vaga Sep 23, 2019
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spec_base_wr.vhd hdl/rtl/spec_base_wr.vhd +15 -4

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--- a/hdl/rtl/spec_base_wr.vhd
+++ b/hdl/rtl/spec_base_wr.vhd
@@ -1011,10 +1011,21 @@ begin  -- architecture top

  --  DDR3 controller
  gen_with_ddr: if g_WITH_DDR generate
+    function get_ddr3_bank_port_select return string is
+    begin
+      case g_DDR_DATA_SIZE is
+        when 32 => return "SPEC_BANK3_32B_32B";
+        when 64 => return "SPEC_BANK3_64B_32B";
+        when others =>
+          assert false report "Invalid g_DDR_DATA_SIZE" severity error;
+          return "error";
+      end case;
+    end get_ddr3_bank_port_select;
+  begin
    cmp_ddr_ctrl_bank3 : entity work.ddr3_ctrl
      generic map(
        g_RST_ACT_LOW        => 0, -- active high reset (simpler internal logic)
-        g_BANK_PORT_SELECT   => "SPEC_BANK3_64B_32B",
+        g_BANK_PORT_SELECT   => get_ddr3_bank_port_select,
        g_MEMCLK_PERIOD      => 3000,
        g_SIMULATION         => boolean'image(g_SIMULATION),
        g_CALIB_SOFT_IP      => "TRUE",